Wafer-level testing is a well established solution for detecting manufacturing errors and removing non-functional devices early in the fabrication process. Recently this technique has been facing a number of challenges, resulting from increased complexity of devices under test, larger number and higher density of pads or bumps, application of mechanically fragile materials, such as low-k dielectrics, and ever developing packaging technologies. Most of these difficulties originate from the use of mechanical probes, as they limit testing speed, impose performance limitations and add reliability issues. Earlier work focused on relaxing these constraints by removing mechanical probes for data transmission and DC signal measurement and replacing them with non-contact interfaces. In this paper we extend this concept by adding a capability of transferring power wirelessly, enabling non-contact wafer-level testing. In addition to further improvements in the performance and reliability, this solution enables new testing scenarios such as probing wafers from their backside. The proposed system achieves 6 W/25 mm2 power transfer density over a distance of up to 0.32 mm, making it suitable for non-contact wafer-level testing of medium performance CMOS integrated circuits.
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Andrzej RADECKI, Hayun CHUNG, Yoichi YOSHIDA, Noriyuki MIURA, Tsunaaki SHIDEI, Hiroki ISHIKURO, Tadahiro KURODA, "6 W/25 mm2 Wireless Power Transmission for Non-contact Wafer-Level Testing" in IEICE TRANSACTIONS on Electronics,
vol. E95-C, no. 4, pp. 668-676, April 2012, doi: 10.1587/transele.E95.C.668.
Abstract: Wafer-level testing is a well established solution for detecting manufacturing errors and removing non-functional devices early in the fabrication process. Recently this technique has been facing a number of challenges, resulting from increased complexity of devices under test, larger number and higher density of pads or bumps, application of mechanically fragile materials, such as low-k dielectrics, and ever developing packaging technologies. Most of these difficulties originate from the use of mechanical probes, as they limit testing speed, impose performance limitations and add reliability issues. Earlier work focused on relaxing these constraints by removing mechanical probes for data transmission and DC signal measurement and replacing them with non-contact interfaces. In this paper we extend this concept by adding a capability of transferring power wirelessly, enabling non-contact wafer-level testing. In addition to further improvements in the performance and reliability, this solution enables new testing scenarios such as probing wafers from their backside. The proposed system achieves 6 W/25 mm2 power transfer density over a distance of up to 0.32 mm, making it suitable for non-contact wafer-level testing of medium performance CMOS integrated circuits.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.668/_p
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@ARTICLE{e95-c_4_668,
author={Andrzej RADECKI, Hayun CHUNG, Yoichi YOSHIDA, Noriyuki MIURA, Tsunaaki SHIDEI, Hiroki ISHIKURO, Tadahiro KURODA, },
journal={IEICE TRANSACTIONS on Electronics},
title={6 W/25 mm2 Wireless Power Transmission for Non-contact Wafer-Level Testing},
year={2012},
volume={E95-C},
number={4},
pages={668-676},
abstract={Wafer-level testing is a well established solution for detecting manufacturing errors and removing non-functional devices early in the fabrication process. Recently this technique has been facing a number of challenges, resulting from increased complexity of devices under test, larger number and higher density of pads or bumps, application of mechanically fragile materials, such as low-k dielectrics, and ever developing packaging technologies. Most of these difficulties originate from the use of mechanical probes, as they limit testing speed, impose performance limitations and add reliability issues. Earlier work focused on relaxing these constraints by removing mechanical probes for data transmission and DC signal measurement and replacing them with non-contact interfaces. In this paper we extend this concept by adding a capability of transferring power wirelessly, enabling non-contact wafer-level testing. In addition to further improvements in the performance and reliability, this solution enables new testing scenarios such as probing wafers from their backside. The proposed system achieves 6 W/25 mm2 power transfer density over a distance of up to 0.32 mm, making it suitable for non-contact wafer-level testing of medium performance CMOS integrated circuits.},
keywords={},
doi={10.1587/transele.E95.C.668},
ISSN={1745-1353},
month={April},}
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TY - JOUR
TI - 6 W/25 mm2 Wireless Power Transmission for Non-contact Wafer-Level Testing
T2 - IEICE TRANSACTIONS on Electronics
SP - 668
EP - 676
AU - Andrzej RADECKI
AU - Hayun CHUNG
AU - Yoichi YOSHIDA
AU - Noriyuki MIURA
AU - Tsunaaki SHIDEI
AU - Hiroki ISHIKURO
AU - Tadahiro KURODA
PY - 2012
DO - 10.1587/transele.E95.C.668
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2012
AB - Wafer-level testing is a well established solution for detecting manufacturing errors and removing non-functional devices early in the fabrication process. Recently this technique has been facing a number of challenges, resulting from increased complexity of devices under test, larger number and higher density of pads or bumps, application of mechanically fragile materials, such as low-k dielectrics, and ever developing packaging technologies. Most of these difficulties originate from the use of mechanical probes, as they limit testing speed, impose performance limitations and add reliability issues. Earlier work focused on relaxing these constraints by removing mechanical probes for data transmission and DC signal measurement and replacing them with non-contact interfaces. In this paper we extend this concept by adding a capability of transferring power wirelessly, enabling non-contact wafer-level testing. In addition to further improvements in the performance and reliability, this solution enables new testing scenarios such as probing wafers from their backside. The proposed system achieves 6 W/25 mm2 power transfer density over a distance of up to 0.32 mm, making it suitable for non-contact wafer-level testing of medium performance CMOS integrated circuits.
ER -