A 10-bit CMOS Digital-to-Analog Converter with Compact Size for Display Applications

Mungyu KIM; Hoon-Ju CHUNG; Young-Chan JANG

doi:10.1587/transele.E97.C.519

A 10-bit CMOS Digital-to-Analog Converter with Compact Size for Display Applications

Mungyu KIM, Hoon-Ju CHUNG, Young-Chan JANG

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A 10-bit digital-to-analog converter (DAC) with a small area is proposed for data-driver integrated circuits of active-matrix liquid crystal display systems. The 10-bit DAC consists of a 7-bit resistor string, a 7-bit two-step decoder, a 2-bit logarithmic time interpolator, and a buffer amplifier. The proposed logarithmic time interpolation is achieved by controlling the charging time of a first-order low-pass filter composed of a resistor and a capacitor. The 7-bit two-step decoder that follows the 7-bit resistor string outputs an analog signal of the stepped wave with two voltage levels using the additional 1-bit digital code for the logarithmic time interpolation. The proposed 10-bit DAC is implemented using a 0.35-µm CMOS process and its supply voltage is scalable from 3.3V to 5.0V. The area of the proposed 10-bit logarithmic time interpolation DAC occupies 57% of that of the conventional 10-bit resistor-string DAC. The DNL and INL of the implemented 10-bit DAC are +0.29/-0.30 and +0.47/-0.36 LSB, respectively.

Publication: IEICE TRANSACTIONS on Electronics Vol.E97-C No.6 pp.519-525

Publication Date: 2014/06/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E97.C.519

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)

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Authors

Mungyu KIM
  Kumoh National Institute of Technology
Hoon-Ju CHUNG
  Kumoh National Institute of Technology
Young-Chan JANG
  Kumoh National Institute of Technology

Keyword

digital-to-analog converter, resistor string, logarithmic time interpolator, low-pass filter, decoder

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Mungyu KIM, Hoon-Ju CHUNG, Young-Chan JANG, "A 10-bit CMOS Digital-to-Analog Converter with Compact Size for Display Applications" in IEICE TRANSACTIONS on Electronics, vol. E97-C, no. 6, pp. 519-525, June 2014, doi: 10.1587/transele.E97.C.519.
Abstract: A 10-bit digital-to-analog converter (DAC) with a small area is proposed for data-driver integrated circuits of active-matrix liquid crystal display systems. The 10-bit DAC consists of a 7-bit resistor string, a 7-bit two-step decoder, a 2-bit logarithmic time interpolator, and a buffer amplifier. The proposed logarithmic time interpolation is achieved by controlling the charging time of a first-order low-pass filter composed of a resistor and a capacitor. The 7-bit two-step decoder that follows the 7-bit resistor string outputs an analog signal of the stepped wave with two voltage levels using the additional 1-bit digital code for the logarithmic time interpolation. The proposed 10-bit DAC is implemented using a 0.35-µm CMOS process and its supply voltage is scalable from 3.3V to 5.0V. The area of the proposed 10-bit logarithmic time interpolation DAC occupies 57% of that of the conventional 10-bit resistor-string DAC. The DNL and INL of the implemented 10-bit DAC are +0.29/-0.30 and +0.47/-0.36 LSB, respectively.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E97.C.519/_p

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@ARTICLE{e97-c_6_519,
author={Mungyu KIM, Hoon-Ju CHUNG, Young-Chan JANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 10-bit CMOS Digital-to-Analog Converter with Compact Size for Display Applications},
year={2014},
volume={E97-C},
number={6},
pages={519-525},
abstract={A 10-bit digital-to-analog converter (DAC) with a small area is proposed for data-driver integrated circuits of active-matrix liquid crystal display systems. The 10-bit DAC consists of a 7-bit resistor string, a 7-bit two-step decoder, a 2-bit logarithmic time interpolator, and a buffer amplifier. The proposed logarithmic time interpolation is achieved by controlling the charging time of a first-order low-pass filter composed of a resistor and a capacitor. The 7-bit two-step decoder that follows the 7-bit resistor string outputs an analog signal of the stepped wave with two voltage levels using the additional 1-bit digital code for the logarithmic time interpolation. The proposed 10-bit DAC is implemented using a 0.35-µm CMOS process and its supply voltage is scalable from 3.3V to 5.0V. The area of the proposed 10-bit logarithmic time interpolation DAC occupies 57% of that of the conventional 10-bit resistor-string DAC. The DNL and INL of the implemented 10-bit DAC are +0.29/-0.30 and +0.47/-0.36 LSB, respectively.},
keywords={},
doi={10.1587/transele.E97.C.519},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - A 10-bit CMOS Digital-to-Analog Converter with Compact Size for Display Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 519
EP - 525
AU - Mungyu KIM
AU - Hoon-Ju CHUNG
AU - Young-Chan JANG
PY - 2014
DO - 10.1587/transele.E97.C.519
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E97-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2014
AB - A 10-bit digital-to-analog converter (DAC) with a small area is proposed for data-driver integrated circuits of active-matrix liquid crystal display systems. The 10-bit DAC consists of a 7-bit resistor string, a 7-bit two-step decoder, a 2-bit logarithmic time interpolator, and a buffer amplifier. The proposed logarithmic time interpolation is achieved by controlling the charging time of a first-order low-pass filter composed of a resistor and a capacitor. The 7-bit two-step decoder that follows the 7-bit resistor string outputs an analog signal of the stepped wave with two voltage levels using the additional 1-bit digital code for the logarithmic time interpolation. The proposed 10-bit DAC is implemented using a 0.35-µm CMOS process and its supply voltage is scalable from 3.3V to 5.0V. The area of the proposed 10-bit logarithmic time interpolation DAC occupies 57% of that of the conventional 10-bit resistor-string DAC. The DNL and INL of the implemented 10-bit DAC are +0.29/-0.30 and +0.47/-0.36 LSB, respectively.
ER -