Extremely low voltage operation near or below threshold voltage is a key circuit technology to improve the energy efficiency of information systems and to realize ultra-low power sensor nodes. However, it is difficult to operate conventional analog circuits based on amplifier at low voltage. Furthermore, PVT (Process, Voltage and Temperature) variation and random V_th variation degrade the minimum operation voltage and the energy efficiency in both digital and analog circuits. In this paper, extremely low power analog circuits based on comparator and switched capacitor as well as extremely low power digital circuits are presented. Many kinds of circuit technologies are applied to cope with the variation problem. Finally, image processing SoC that integrates digital and analog circuits is presented, where improvement of total performance by a cooperation of analog circuits and digital circuits is demonstrated.

E-band communication is allocated to the frequency bands of 71-76 and 81-86GHz. Radio-frequency (RF) front-end components for E-band communication have been realized using compound semiconductor technology. To realize a CMOS LNA for E-band communication, we propose a gain-boosted cascode amplifier (GBCA) stage that simultaneously provides high gain and stability. Designing an LNA from scratch requires considerable time because the tuning of matching networks with consideration of the parasitic elements is complicated. In this paper, we model the characteristics of devices including the effects of their parasitic elements. Using these models, an optimizer can estimate the characteristic of a designed LNA precisely without electromagnetic simulations and gives us the design values of an LNA when the layout constraint is ignored. Starting from the values, a four-stage LNA with a GBCA stage is designed very easily even though the layout constraint is considered and fabricated by a 65nm LP CMOS process. The fabricated LNA is measured, and it is confirmed that it achieves 18.5GHz bandwidth and over 24.3dB gain with 50.6mW power consumption. This is the first LNA to achieve a gain bandwidth of over 300GHz in the E-band among the LNAs utilizing any kind of semiconductor technologies. In this paper, we have proved that CMOS technology, which is suitable for baseband and digital circuitry, is applicable to a communication system covering the entire E-band.

In this paper, we present a differential dual-modulus prescaler based on an injection-locked frequency divider (ILFD) for satellite low-noise block (LNB) down-converters. We fabricated three-stage differential latches using an ILFD and a cascaded differential divider in a 130-nm CMOS process. The prototype chip core area occupies 40µm × 20µm. The proposed prescaler achieved the locking range of 2.1-10GHz with both divide-by-10 and divide-by-11 operations at a supply voltage of 1.4V. Normalized energy consumptions are 0.4pJ (=mW/GHz) at a 1.4-V supply voltage and 0.24pJ at a 1.2-V supply voltage. To evaluate the tolerance of phase-difference deviation of the input differential pair from the perfect differential phase-difference, 180 degrees, we measured the operational frequencies for various phase-difference inputs. The proposed prescaler achieved the operational frequency range of 2.1-10GHz with an input phase-difference deviation of less than 90 degrees. However, the range of operational frequency decreases as the phase-difference deviation increases beyond 90 degrees and reaches 3.9-7.9GHz for the phase-difference deviation of 180 degrees (i.e. no phase difference). In addition, to confirm the fully locking operation, we measured the spurious noise and the phase noise degradation while reducing the supply voltage. The sensitivity analysis of the prescaler for various supply voltages can explain the above degradation of spectral purity. Spurious noise arises and the phase noise degrades with decreasing supply voltage due to the quasi- and non-locking operations. We verified the fully-locking operation for the LNB down-converter at a 1.4-V supply voltage.

This paper proposes an ultra-low-power 5.5-GHz PLL which employs the new divide-by-4 injection-locked frequency divider (ILFD) and a class-C VCO with linearity-compensated varactor for low supply voltage operation. A forward-body-biasing (FBB) technique can decrease threshold voltage of MOS transistors, which can improve operation frequency and can widen the lock range of the ILFD. The FBB is also employed for linear-frequency-tuning of VCO under low supply voltage of 0.5V. The double-switch injection technique is also proposed to widen the lock range of the ILFD. The digital calibration circuit is introduced to control the lock-range of ILFD automatically. The proposed PLL was fabricated in a 65nm CMOS process. With a 34.3-MHz reference, it shows a 1-MHz-offset phase noise of -106dBc/Hz at 5.5GHz output. The supply voltage is 0.54V for divider and 0.5V for other components. Total power consumption is 0.95mW.

Parametric resonance based solutions for sub-gigahertz radio frequency transceiver with 0.3V supply voltage are proposed in this paper. As an implementation example, a 0.3V 720µW variation-tolerant injection-locked frequency multiplier is developed in 90nm CMOS. It features a parametric resonance based multi-phase synthesis scheme, thereby achieving the lowest supply voltage with -110dBc@ 600kHz phase noise and 873MHz-1.008GHz locking range in state-of-the-art frequency synthesizers.

A fully on-chip CMOS relaxation oscillator (ROSC) with a PVT variation compensation circuit is proposed in this paper. The circuit is based on a conventional ROSC and has a distinctive feature in the compensation circuit that compensates for comparator's non-idealities caused by not only offset voltage, but also delay time. Measurement results demonstrated that the circuit can generate a stable clock frequency of 6.66kHz. The current dissipation was 320nA at 1.0-V power supply. The measured line regulation and temperature coefficient were 0.98%/V and 56ppm/°C, respectively.

A 10-bit digital-to-analog converter (DAC) with a small area is proposed for data-driver integrated circuits of active-matrix liquid crystal display systems. The 10-bit DAC consists of a 7-bit resistor string, a 7-bit two-step decoder, a 2-bit logarithmic time interpolator, and a buffer amplifier. The proposed logarithmic time interpolation is achieved by controlling the charging time of a first-order low-pass filter composed of a resistor and a capacitor. The 7-bit two-step decoder that follows the 7-bit resistor string outputs an analog signal of the stepped wave with two voltage levels using the additional 1-bit digital code for the logarithmic time interpolation. The proposed 10-bit DAC is implemented using a 0.35-µm CMOS process and its supply voltage is scalable from 3.3V to 5.0V. The area of the proposed 10-bit logarithmic time interpolation DAC occupies 57% of that of the conventional 10-bit resistor-string DAC. The DNL and INL of the implemented 10-bit DAC are +0.29/-0.30 and +0.47/-0.36 LSB, respectively.

A third-order low-distortion delta-sigma modulator (DSM), whose third-order noise-shaping ability is achieved by just a single opamp, is proposed. Since only one amplifier is required in the whole circuit, the designed DSM is very power efficient. To realize the adder in front of quantizer without employing the huge-power opamp, a capacitive passive adder, which is the digital-to-analog converter (DAC) array of a successive-approximation-type quantizer, is used. In addition, the feedback path timing is extended from a nonoverlapping interval for the conventional low-distortion structure to half of the clock period, so that the strict operation timing issue with regard to quantization and the dynamic element matching (DEM) logic operation can be solved. In the proposed DSM structure, the features of the unity-gain signal transfer function (STF) and finite-impulse-response (FIR) noise transfer function (NTF) are still preserved, and thus advantages such as a relaxed opamp slew rate and reduced output swing are also maintained, as with the conventional low-distortion DSM. Moreover, the memory effect in the proposed DSM is analyzed when employing the opamp sharing for integrators. The proposed third-order DSM with a 4-bit SAR ADC as the quantizer is implemented in a 90-nm CMOS process. The post-layout simulations show a 79.8-dB signal-to-noise and distortion ratio (SNDR) in the 1.875-MHz signal bandwidth (OSR=16). The active area of the circuit is 0.35mm² and total power consumption is 2.85mW, resulting in a figure of merit (FOM) of 95 fJ/conversion-step.

The proposed stimulus design for linearity test is embedded in a differential successive approximation register analog-to-digital converter (SAR ADC), i.e. a design for testability (DFT). The proposed DFT is compatible to the pattern generator (PG) and output response analyzer (ORA) with the cost of 12.4-% area of the SAR ADC. The 10-bit SAR ADC prototype is verified in a 0.18-µm CMOS technology and the measured differential nonlinearity (DNL) error is between -0.386 and 0.281 LSB at 1-MS/s.

Substrate noise coupling in RF receiver front-end circuitry for LTE wireless communication was examined by full-chip level simulation and on-chip measurements, with a demonstrator built in a 65nm CMOS technology. A CMOS digital noise emulator injects high-order harmonic noises in a silicon substrate and induces in-band spurious tones in an RF receiver on the same chip through substrate noise interference. A complete simulation flow of full-chip level substrate noise coupling uses a decoupled modeling approach, where substrate noise waveforms drawn with a unified package-chip model of noise source circuits are given to mixed-level simulation of RF chains as noise sensitive circuits. The distribution of substrate noise in a chip and the attenuation with distance are simulated and compared with the measurements. The interference of substrate noise at the 17th harmonics of 124.8MHz — the operating frequency of the CMOS noise emulator creates spurious tones in the communication bandwidth at 2.1GHz.

A three dimensional (3D) chip stack featuring a 4096-bit wide I/O demonstrator incorporates an in-place waveform capturer on an intermediate interposer within the stack. The capturer includes probing channels on paths of signaling as well as in power delivery and collects analog waveforms for diagnosing circuits within 3D integration. The collection of in-place waveforms on vertical channels with through silicon vias (TSVs) are demonstrated among 128 vertical I/O channels distributed in 8 banks in a 9.9mm × 9.9mm die area. The analog waveforms confirm a full 1.2-V swing of signaling at the maximum data transmission bandwidth of 100GByte/sec with sufficiently small deviations of signal skews and slews among the vertical channels. In addition, it is also experimentally confirmed that the signal swing can be reduced to 0.75V for error free data transfer at 100GByte/sec, achieving the energy efficiency of 0.21pJ/bit.

Polarimetric coherence strongly relates to the types and orientations of local scatterers. An optimization scheme is proposed to optimize the coherence between two polarimetric channels for polarimetric SAR (PolSAR) data. The coherence magnitude (correlation coefficient) is maximized by rotating a polarimetric coherence matrix in the rotation domain around the radar line of sight. L-band E-SAR and X-band Pi-SAR PolSAR data sets are used for demonstration and validation. The coherence of oriented manmade targets is significantly enhanced while that of forests remains relatively low. Therefore, the proposed technique can effectively discriminate these two land covers which are easily misinterpreted by the conventional model-based decomposition. Moreover, based on an optimized polarimetric coherence parameter and the total backscattered power, a simple manmade target extraction scheme is developed for application demonstration. This approach is applied with the Pi-SAR data. The experimental results validate the effectiveness of the proposed method.

Four calculation techniques for the Q-factor determination of resonant structures are compared on the basis of the influence of the VNA measurement uncertainty. The influence is evaluated using Monte Carlo calculations. On the basis of the deviation, the dispersion, and the effect of nearby resonances, the circle fitting method is the most appropriate technique. Although the 3dB method is the most popular technique, the Q-factors calculated by this method exhibit deviations, and the sign and amount of the deviation depend on the measurement setup. Comparisons using measurement data demonstrate that the uncertainty of the dielectric loss tangent calculated by the circle fitting method is less than a third of those calculated by the other three techniques.

This paper presents a 120-GHz-band amplifier module with a hermetic sealing structure for a broadband wireless system. The sealing structure for F-band waveguides is a laminate composed of two sealing plates and a spacer. Each sealing plate has a fused glass window and separates inside air from the ambient atmosphere. The design process of the sealing structure is simple and has good simulation fidelity. The hermetic sealing structure designed for an amplifier in a 120-GHz-band wireless link has an insertion loss of less than 1dB and a return loss of more than 15dB in the operating band. We made three kinds of sealed modules to evaluate the sealing function. The modules sealed with this technique meet the hermetic-seal standard in MIL-STD-883F. We then verified that the sealing structure on the sealed modules has a small enough effect for the transmittance of the intrinsic characteristics. In addition, we performed 10-Gbit/s data transmission using a sealed amplifier module with the bit error rate of less than 10^-10.

Break arcs are generated in a DC48V and 12A resistive circuit. Silver electrical contacts are separated at constant opening speed. The cathode contact surface is irradiated by a blue LED. The center wavelength of the emission of the LED is 470nm. There is no spectral line of the light emitted from the break arcs. Only the images of contact surface are observed by a high-speed camera and an optical band pass filter. Another high-speed camera observes only the images of the break arc. Time evolutions of the cathode surface morphology being eroded by the break arcs and the motion of the break arcs are observed with these cameras, simultaneously. The images of the cathode surface are investigated by the image analysis technique. The results show that the moments when the expanded regions on the cathode surface are formed during the occurrence of the break arcs. In addition, it is shown that the expanded regions are not contacted directly to the cathode roots of the break arcs.

One of the technological innovations that has enabled the VLSI semiconductor industry to reduce the transistor size, increase the number of transistors per die, and also follow Moore's law year after year is the fact that an equivalent yield and equivalent testing quality have been ensured for the same die size. This has contributed to reducing the economically optimum production cost (production cost per component) as advocated by Moore. In this paper, we will verify Moore's law using actual values from VLSI manufacturing sites while introducing some of the technical progress that occurred from 1970 to 2010.

Yield enhancements and quality improvements must be considered as factors of the utmost importance in VLSI (Very Large Scale Integration circuits) manufacturing in order to reduce cost and ensure customer satisfaction. This paper will present a study of the yield theory, an analysis of actual manufacturing data, and the challenges of yield enhancement.

An RGB-LED driver with a pulse-skipping-modulation boost converter is proposed to fix the reference voltage for lowering down the circuit complexity. A high-voltage LDO and a bandgap reference circuit are built into the chip. The proposed converter outputs a different voltage in response to a different color of LEDs. The output voltages for driving six red, six green, and six blue LEDs in series are 13.5V, 20V, and 21.5V, respectively. The proposed LDO and bandgap reference circuit work with supply voltages from 8V to 12V. The settling time for changing colors is lower than 300µs, better than the unfixed-reference-voltage methods. The proposed circuit was fabricated by using 0.25-µm BCD 60V technology, and the chip area was 1.9 × 1.7mm².