Technology of FinFET for High RF and Analog/Mixed-Signal Performance Circuits

Tatsuya OHGURO; Satoshi INABA; Akio KANEKO; Kimitoshi OKANO

doi:10.1587/transele.E98.C.455

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Technology of FinFET for High RF and Analog/Mixed-Signal Performance Circuits

Tatsuya OHGURO, Satoshi INABA, Akio KANEKO, Kimitoshi OKANO

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In this paper, we discuss the process, layout and device technologies of FinFET to obtain high RF and analog/mixed-signal performance circuits. The fin patterning due to Side-wall transfer (SWT) technique is useful to not only fabricate narrow fin line but also suppress the fin width variation comparing with ArF and EB lithography. The H₂ annealing after Si etching is useful for not only to improve the mobility of electron and hole but also to reduce flicker noise of FinFET. The noise decreases as the scaling of fin width and that of FinFET with below 50 nm fin width is satisfied with the requirement from 25 nm technology node in ITRS roadmap 2013. This lower noise is attributed to the decrease of electric field from the channel to the gate electrode. Additionally, the optimum layout of FinFET is discussed for RF performance. In order to obtain higher f_T and f_max, it is necessary to have the optimized finger length and reduced capacitances between the gate and Si substrate and between gate and source, drain contact region. According to our estimation, the f_T of FinFET with the optimized layout should be lower than that of planar MOSFET when the gate length is longer than 10 nm due to larger gate capacitance. In conclusion, FinFET is suitable for high performance digital and analog/mixed-signal circuits. On the other hand, planar MOSFET is better rather than FinFET for RF circuits.

Publication: IEICE TRANSACTIONS on Electronics Vol.E98-C No.6 pp.455-460

Publication Date: 2015/06/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E98.C.455

Type of Manuscript: Special Section INVITED PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)

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Authors

Tatsuya OHGURO
  Toshiba Corporation
Satoshi INABA
  Toshiba Corporation
Akio KANEKO
  Toshiba Corporation
Kimitoshi OKANO
  Toshiba Corporation

Keyword

FinFET, analog, RF, flicker noise, f_T, f_max

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Tatsuya OHGURO, Satoshi INABA, Akio KANEKO, Kimitoshi OKANO, "Technology of FinFET for High RF and Analog/Mixed-Signal Performance Circuits" in IEICE TRANSACTIONS on Electronics, vol. E98-C, no. 6, pp. 455-460, June 2015, doi: 10.1587/transele.E98.C.455.
Abstract: In this paper, we discuss the process, layout and device technologies of FinFET to obtain high RF and analog/mixed-signal performance circuits. The fin patterning due to Side-wall transfer (SWT) technique is useful to not only fabricate narrow fin line but also suppress the fin width variation comparing with ArF and EB lithography. The H₂ annealing after Si etching is useful for not only to improve the mobility of electron and hole but also to reduce flicker noise of FinFET. The noise decreases as the scaling of fin width and that of FinFET with below 50 nm fin width is satisfied with the requirement from 25 nm technology node in ITRS roadmap 2013. This lower noise is attributed to the decrease of electric field from the channel to the gate electrode. Additionally, the optimum layout of FinFET is discussed for RF performance. In order to obtain higher f_T and f_max, it is necessary to have the optimized finger length and reduced capacitances between the gate and Si substrate and between gate and source, drain contact region. According to our estimation, the f_T of FinFET with the optimized layout should be lower than that of planar MOSFET when the gate length is longer than 10 nm due to larger gate capacitance. In conclusion, FinFET is suitable for high performance digital and analog/mixed-signal circuits. On the other hand, planar MOSFET is better rather than FinFET for RF circuits.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E98.C.455/_p

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@ARTICLE{e98-c_6_455,
author={Tatsuya OHGURO, Satoshi INABA, Akio KANEKO, Kimitoshi OKANO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Technology of FinFET for High RF and Analog/Mixed-Signal Performance Circuits},
year={2015},
volume={E98-C},
number={6},
pages={455-460},
abstract={In this paper, we discuss the process, layout and device technologies of FinFET to obtain high RF and analog/mixed-signal performance circuits. The fin patterning due to Side-wall transfer (SWT) technique is useful to not only fabricate narrow fin line but also suppress the fin width variation comparing with ArF and EB lithography. The H₂ annealing after Si etching is useful for not only to improve the mobility of electron and hole but also to reduce flicker noise of FinFET. The noise decreases as the scaling of fin width and that of FinFET with below 50 nm fin width is satisfied with the requirement from 25 nm technology node in ITRS roadmap 2013. This lower noise is attributed to the decrease of electric field from the channel to the gate electrode. Additionally, the optimum layout of FinFET is discussed for RF performance. In order to obtain higher f_T and f_max, it is necessary to have the optimized finger length and reduced capacitances between the gate and Si substrate and between gate and source, drain contact region. According to our estimation, the f_T of FinFET with the optimized layout should be lower than that of planar MOSFET when the gate length is longer than 10 nm due to larger gate capacitance. In conclusion, FinFET is suitable for high performance digital and analog/mixed-signal circuits. On the other hand, planar MOSFET is better rather than FinFET for RF circuits.},
keywords={},
doi={10.1587/transele.E98.C.455},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - Technology of FinFET for High RF and Analog/Mixed-Signal Performance Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 455
EP - 460
AU - Tatsuya OHGURO
AU - Satoshi INABA
AU - Akio KANEKO
AU - Kimitoshi OKANO
PY - 2015
DO - 10.1587/transele.E98.C.455
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E98-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2015
AB - In this paper, we discuss the process, layout and device technologies of FinFET to obtain high RF and analog/mixed-signal performance circuits. The fin patterning due to Side-wall transfer (SWT) technique is useful to not only fabricate narrow fin line but also suppress the fin width variation comparing with ArF and EB lithography. The H₂ annealing after Si etching is useful for not only to improve the mobility of electron and hole but also to reduce flicker noise of FinFET. The noise decreases as the scaling of fin width and that of FinFET with below 50 nm fin width is satisfied with the requirement from 25 nm technology node in ITRS roadmap 2013. This lower noise is attributed to the decrease of electric field from the channel to the gate electrode. Additionally, the optimum layout of FinFET is discussed for RF performance. In order to obtain higher f_T and f_max, it is necessary to have the optimized finger length and reduced capacitances between the gate and Si substrate and between gate and source, drain contact region. According to our estimation, the f_T of FinFET with the optimized layout should be lower than that of planar MOSFET when the gate length is longer than 10 nm due to larger gate capacitance. In conclusion, FinFET is suitable for high performance digital and analog/mixed-signal circuits. On the other hand, planar MOSFET is better rather than FinFET for RF circuits.
ER -