In this paper, we discuss the process, layout and device technologies of FinFET to obtain high RF and analog/mixed-signal performance circuits. The fin patterning due to Side-wall transfer (SWT) technique is useful to not only fabricate narrow fin line but also suppress the fin width variation comparing with ArF and EB lithography. The H₂ annealing after Si etching is useful for not only to improve the mobility of electron and hole but also to reduce flicker noise of FinFET. The noise decreases as the scaling of fin width and that of FinFET with below 50 nm fin width is satisfied with the requirement from 25 nm technology node in ITRS roadmap 2013. This lower noise is attributed to the decrease of electric field from the channel to the gate electrode. Additionally, the optimum layout of FinFET is discussed for RF performance. In order to obtain higher f_T and f_max, it is necessary to have the optimized finger length and reduced capacitances between the gate and Si substrate and between gate and source, drain contact region. According to our estimation, the f_T of FinFET with the optimized layout should be lower than that of planar MOSFET when the gate length is longer than 10 nm due to larger gate capacitance. In conclusion, FinFET is suitable for high performance digital and analog/mixed-signal circuits. On the other hand, planar MOSFET is better rather than FinFET for RF circuits.

In this paper, the importance and perspective for the digitally-assisted analog and RF circuits are discussed, especially related to wireless transceivers. Digital calibration techniques for compensating I/Q mismatch, IM2, and LO impairments in cellular, 2.4 GHz WiFi, and 60 GHz WiGig transceivers are introduced with detailed analysis and circuit implementations. Future technology directions such as the shift from digitally-assisted analog circuit to digitally-designed analog circuit will also be discussed.

This paper presents a constant-current-controlled class-C VCO using a self-adjusting replica bias circuit. The proposed class-C VCO is more suitable in real-life applications as it can maintain constant current which is more robust in phase noise performance over variation of gate bias of cross-coupled pair comparing to a traditional approach without amplitude modulation issue. The proposed VCO is implemented in 180 nm CMOS process. It achieves a tuning range of 4.8–4.9 GHz with a phase noise of -121 dBc/Hz at 1 MHz offset. The power consumption of the core oscillators is 4.8 mW and an FoM of -189 dBc/Hz is achieved.

This work presents a novel counter-based randomization method for use in a flying-adder frequency synthesizer with a cost-effective structure that can replace the fractional accumulator. The proposed technique involves a counter, a comparator and a modified linear feedback shift register. The power consumption and speed bottleneck of the conventional flying-adder are significantly reduced. The modified linear shift feedback register is used as a pseudo random data generator, suppressing the spurious tones arise from the periodic carry sequences that is generated by the fractional accumulator. Furthermore, the proposed counter-based randomization method greatly reduces the large memory size that is required by the conventional approach to carry randomization. A test chip for the proposed counter-based randomization method is fabricated in the TSMC 0.18 μm 1P6M CMOS process, with the core area of 0.093 mm². The output frequency had a range of 43.4 MHz ∼ 225.8 MHz at 1.8 V with peak-to-peak jitter (Pk-Pk) jitter 139.2 ps at 225.8 MHz. Power consumption is 2.8 mW @ 225.8 MHz with 1.8 supply voltage.

We present an I/O-size second-order analog to digital converter (ADC) combined with a time-to-digital converter (TDC) and a voltage-to-time converter (VTC). Our proposed VTC is optimized for metal–oxide–metal (MOM) capacitances, and is charged to the MOM capacitances by an input voltage. In a standard 65-nm CMOS process, a signal to noise and distortion ratio (SNDR) of 50 dB (8 bits) is achievable at an input signal frequency of 78 kHz and a sampling rate of 20 MHz, where the respective area and power are 6468 mm² and 509 μW. The measured maximum integral nonlinearity (INL) of the proposed ADC is -1.41 LSBs. The active area of the proposed ADC is smaller than an I/O buffer. The proposed ADC is useful as an ADC I/O.

A current mode buck/boost DC-DC converter with automatic mode transition is presented in this paper. At heavy load, a control scheme adaptively changes operation mode between peak and valley current modes to achieve high efficiency, small output voltage ripple, and fast transient response. The switching loss is reduced by operating in pure modes, and the conduction loss is reduced by decreasing the average inductor current in transition modes. At light load, the equivalent switching frequency is decreased to reduce the switching loss. An automatic mode transition between heavy load PWM mode and light load PFM mode is achieved by introducing an average load current sensing method. The converter has been implemented with a standard 0.5 μm CMOS process. The output voltage ripple is less than 10 mV in all modes, and the peak efficiency is 95%.

A forward/reverse body bias generator (BBG) which operates under wide supply-range is proposed. Fine-grained body biasing (FGBB) is effective to reduce variability and increase energy efficiency on digital LSIs. Since FGBB requires a number of BBGs to be implemented, simple design is preferred. We propose a BBG with charge pumps for reverse body bias and the BBG operates under wide supply-range from 0.5 V to 1.2 V. Layout of the BBG was designed in a cell-based flow with an AES core and fabricated in a 65 nm CMOS process. Area of the AES core is 0.22 mm² and area overhead of the BBG is 2.3%. Demonstration of the AES core shows a successful operation with the supply voltage from 0.5 V to 1.2 V which enables the reduction of power dissipation, for example, of 17% at 400 MHz operation.

A novel method was developed to expand and adjust the bandwidth of long-period fiber gratings (LPFGs) as band-rejection filters. The band-rejection filters were constructed by concatenating two LPFGs with an appropriate space, that causes a π-phase shift. The component LPFGs with the same period and the different numbers of periods are designed to have -3-dB transmission at wavelengths on both sides of a resonance wavelength symmetrically, and the transmission loss of the concatenated LPFGs peaks at the -3-dB transmission wavelengths. The rejection bandwidth was widened by changing the interval between the -3-dB transmission wavelengths. The concatenated LPFGs were simulated by using a transfer-matrix method based on a discrete coupling model, and were fabricated by a point-by-point arc discharge technique on the basis of the simulation results. It was demonstrated that the rejection bandwidth at 20-dB attenuation reached 26.6 nm and was 2.7 times broader than that of a single uniform LPFG.

As is well known in the design of transformer isolated converters, the transformer leakage inductance causes a large voltage overshoot on the secondary side switching nodes at every switch transition, unless measures are taken to limit the peak voltage stress. Since the peak voltage stress in smart-power integrated converters, where the power devices are integrated on the same die as the controlling logic and supporting circuits, is the major determining factor for the required silicon area for the implementation, this is a major roadblock for the affordable integration of this type of converter. Therefore, any cost-effective smart-power synchronous rectifier requires a voltage clamping circuit that minimizes the voltage stress, while still maintaining the potential advantages of smart-power converters, i.e. minimizing the number and size of the discrete components in the converter. We present an integrated asynchronous active clamping circuit, that can clamp the overshoot voltage to arbitrary voltages while optimizing the efficiency by only being active when required. Because of the asynchronous operation, the size of the required external components is minimized. Measurements on the smart-power IC implementation of the asynchronous active clamp circuit combined with a secondary side synchronous rectifier for a 1 MHz full bridge converter confirm the reduction in voltage stress and the optimization of the efficiency.

In bit-patterned media recording (BPMR), the readback signal is severely corrupted by the inter-symbol interference (ISI) and inter-track interference (ITI), especially at high recording densities, due to small bit and track pitches. One way to alleviate the ITI effect is to encode an input data sequence before recording, so as to avoid some data patterns that easily cause an error at the data detection process. This paper proposes an ITI-mitigating 5/6 modulation code for a multi-track multi-head BPMR system to eliminate the data patterns that lead to severe ITI. Specifically, each of the 5 user bits is converted into a 6-bit codeword in the form of a 3-by-2 data array, based on a look-up table. Experimental results indicate that the system with the proposed coding scheme outperforms that without coding, especially when an areal density is high and/or the position jitter is large.