Flying-Adder Frequency Synthesizer with a Novel Counter-Based Randomization Method

Pao-Lung CHEN; Da-Chen LEE; Wei-Chia LI

doi:10.1587/transele.E98.C.480

Flying-Adder Frequency Synthesizer with a Novel Counter-Based Randomization Method

Pao-Lung CHEN, Da-Chen LEE, Wei-Chia LI

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This work presents a novel counter-based randomization method for use in a flying-adder frequency synthesizer with a cost-effective structure that can replace the fractional accumulator. The proposed technique involves a counter, a comparator and a modified linear feedback shift register. The power consumption and speed bottleneck of the conventional flying-adder are significantly reduced. The modified linear shift feedback register is used as a pseudo random data generator, suppressing the spurious tones arise from the periodic carry sequences that is generated by the fractional accumulator. Furthermore, the proposed counter-based randomization method greatly reduces the large memory size that is required by the conventional approach to carry randomization. A test chip for the proposed counter-based randomization method is fabricated in the TSMC 0.18 μm 1P6M CMOS process, with the core area of 0.093 mm². The output frequency had a range of 43.4 MHz ∼ 225.8 MHz at 1.8 V with peak-to-peak jitter (Pk-Pk) jitter 139.2 ps at 225.8 MHz. Power consumption is 2.8 mW @ 225.8 MHz with 1.8 supply voltage.

Publication: IEICE TRANSACTIONS on Electronics Vol.E98-C No.6 pp.480-488

Publication Date: 2015/06/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E98.C.480

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)

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Authors

Pao-Lung CHEN
  National Kaohsiung First University of Science and Technology
Da-Chen LEE
  National Kaohsiung First University of Science and Technology
Wei-Chia LI
  National Kaohsiung First University of Science and Technology

Keyword

Flying-adder frequency synthesizer, Linear feedback shift register (LFSR), Direct digital period synthesizer (DDPS), accumulator, Digitally controlled oscillator (DCO)

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Pao-Lung CHEN, Da-Chen LEE, Wei-Chia LI, "Flying-Adder Frequency Synthesizer with a Novel Counter-Based Randomization Method" in IEICE TRANSACTIONS on Electronics, vol. E98-C, no. 6, pp. 480-488, June 2015, doi: 10.1587/transele.E98.C.480.
Abstract: This work presents a novel counter-based randomization method for use in a flying-adder frequency synthesizer with a cost-effective structure that can replace the fractional accumulator. The proposed technique involves a counter, a comparator and a modified linear feedback shift register. The power consumption and speed bottleneck of the conventional flying-adder are significantly reduced. The modified linear shift feedback register is used as a pseudo random data generator, suppressing the spurious tones arise from the periodic carry sequences that is generated by the fractional accumulator. Furthermore, the proposed counter-based randomization method greatly reduces the large memory size that is required by the conventional approach to carry randomization. A test chip for the proposed counter-based randomization method is fabricated in the TSMC 0.18 μm 1P6M CMOS process, with the core area of 0.093 mm². The output frequency had a range of 43.4 MHz ∼ 225.8 MHz at 1.8 V with peak-to-peak jitter (Pk-Pk) jitter 139.2 ps at 225.8 MHz. Power consumption is 2.8 mW @ 225.8 MHz with 1.8 supply voltage.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E98.C.480/_p

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@ARTICLE{e98-c_6_480,
author={Pao-Lung CHEN, Da-Chen LEE, Wei-Chia LI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Flying-Adder Frequency Synthesizer with a Novel Counter-Based Randomization Method},
year={2015},
volume={E98-C},
number={6},
pages={480-488},
abstract={This work presents a novel counter-based randomization method for use in a flying-adder frequency synthesizer with a cost-effective structure that can replace the fractional accumulator. The proposed technique involves a counter, a comparator and a modified linear feedback shift register. The power consumption and speed bottleneck of the conventional flying-adder are significantly reduced. The modified linear shift feedback register is used as a pseudo random data generator, suppressing the spurious tones arise from the periodic carry sequences that is generated by the fractional accumulator. Furthermore, the proposed counter-based randomization method greatly reduces the large memory size that is required by the conventional approach to carry randomization. A test chip for the proposed counter-based randomization method is fabricated in the TSMC 0.18 μm 1P6M CMOS process, with the core area of 0.093 mm². The output frequency had a range of 43.4 MHz ∼ 225.8 MHz at 1.8 V with peak-to-peak jitter (Pk-Pk) jitter 139.2 ps at 225.8 MHz. Power consumption is 2.8 mW @ 225.8 MHz with 1.8 supply voltage.},
keywords={},
doi={10.1587/transele.E98.C.480},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - Flying-Adder Frequency Synthesizer with a Novel Counter-Based Randomization Method
T2 - IEICE TRANSACTIONS on Electronics
SP - 480
EP - 488
AU - Pao-Lung CHEN
AU - Da-Chen LEE
AU - Wei-Chia LI
PY - 2015
DO - 10.1587/transele.E98.C.480
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E98-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2015
AB - This work presents a novel counter-based randomization method for use in a flying-adder frequency synthesizer with a cost-effective structure that can replace the fractional accumulator. The proposed technique involves a counter, a comparator and a modified linear feedback shift register. The power consumption and speed bottleneck of the conventional flying-adder are significantly reduced. The modified linear shift feedback register is used as a pseudo random data generator, suppressing the spurious tones arise from the periodic carry sequences that is generated by the fractional accumulator. Furthermore, the proposed counter-based randomization method greatly reduces the large memory size that is required by the conventional approach to carry randomization. A test chip for the proposed counter-based randomization method is fabricated in the TSMC 0.18 μm 1P6M CMOS process, with the core area of 0.093 mm². The output frequency had a range of 43.4 MHz ∼ 225.8 MHz at 1.8 V with peak-to-peak jitter (Pk-Pk) jitter 139.2 ps at 225.8 MHz. Power consumption is 2.8 mW @ 225.8 MHz with 1.8 supply voltage.
ER -