25-Gbps/ch Error-Free Operation over 300-m MMF of Low-Power-Consumption Silicon-Photonics-Based Chip-Scale Optical I/O Cores

Kenichiro YASHIKI; Toshinori UEMURA; Mitsuru KURIHARA; Yasuyuki SUZUKI; Masatoshi TOKUSHIMA; Yasuhiko HAGIHARA; Kazuhiko KURATA

doi:10.1587/transele.E99.C.148

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25-Gbps/ch Error-Free Operation over 300-m MMF of Low-Power-Consumption Silicon-Photonics-Based Chip-Scale Optical I/O Cores

Kenichiro YASHIKI, Toshinori UEMURA, Mitsuru KURIHARA, Yasuyuki SUZUKI, Masatoshi TOKUSHIMA, Yasuhiko HAGIHARA, Kazuhiko KURATA

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Aiming to solve the input/output (I/O) bottleneck concerning next-generation interconnections, 5×5-millimeters-squared silicon-photonics-based chip-scale optical transmitters/receivers (TXs/RXs) — called “optical I/O cores” — were developed. In addition to having a compact footprint, by employing low-power-consumption integrated circuits (ICs), as well as providing multimode-fiber (MMF) transmission in the O band and a user-friendly interface, the developed optical I/O cores allow common ease of use with applications such as multi-chip modules (MCMs) and active optical cables (AOCs). The power consumption of their hybrid-integrated ICs is 5mW/Gbps. Their high-density user-friendly optical interface has a spot-size-converter (SSC) function and permits the physical contact against the outer waveguides. As a result, they provide large enough misalignment tolerance to allow use of passive alignment and visual alignment. In a performance test, they demonstrated 25-Gbps/ch error-free operation over 300-m MMF.

Publication: IEICE TRANSACTIONS on Electronics Vol.E99-C No.2 pp.148-156

Publication Date: 2016/02/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E99.C.148

Type of Manuscript: Special Section INVITED PAPER (Special Section on Recent Advances in Photonics Technologies and Their Applications)

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Authors

Kenichiro YASHIKI
  Photonics Electronics Technology Research Association (PETRA)
Toshinori UEMURA
  Photonics Electronics Technology Research Association (PETRA)
Mitsuru KURIHARA
  Photonics Electronics Technology Research Association (PETRA)
Yasuyuki SUZUKI
  Photonics Electronics Technology Research Association (PETRA)
Masatoshi TOKUSHIMA
  Photonics Electronics Technology Research Association (PETRA)
Yasuhiko HAGIHARA
  Photonics Electronics Technology Research Association (PETRA)
Kazuhiko KURATA
  Photonics Electronics Technology Research Association (PETRA)

Keyword

Si photonics, low-power-consumption, small footprint, high density interface, I/O bottleneck

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Kenichiro YASHIKI, Toshinori UEMURA, Mitsuru KURIHARA, Yasuyuki SUZUKI, Masatoshi TOKUSHIMA, Yasuhiko HAGIHARA, Kazuhiko KURATA, "25-Gbps/ch Error-Free Operation over 300-m MMF of Low-Power-Consumption Silicon-Photonics-Based Chip-Scale Optical I/O Cores" in IEICE TRANSACTIONS on Electronics, vol. E99-C, no. 2, pp. 148-156, February 2016, doi: 10.1587/transele.E99.C.148.
Abstract: Aiming to solve the input/output (I/O) bottleneck concerning next-generation interconnections, 5×5-millimeters-squared silicon-photonics-based chip-scale optical transmitters/receivers (TXs/RXs) — called “optical I/O cores” — were developed. In addition to having a compact footprint, by employing low-power-consumption integrated circuits (ICs), as well as providing multimode-fiber (MMF) transmission in the O band and a user-friendly interface, the developed optical I/O cores allow common ease of use with applications such as multi-chip modules (MCMs) and active optical cables (AOCs). The power consumption of their hybrid-integrated ICs is 5mW/Gbps. Their high-density user-friendly optical interface has a spot-size-converter (SSC) function and permits the physical contact against the outer waveguides. As a result, they provide large enough misalignment tolerance to allow use of passive alignment and visual alignment. In a performance test, they demonstrated 25-Gbps/ch error-free operation over 300-m MMF.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E99.C.148/_p

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@ARTICLE{e99-c_2_148,
author={Kenichiro YASHIKI, Toshinori UEMURA, Mitsuru KURIHARA, Yasuyuki SUZUKI, Masatoshi TOKUSHIMA, Yasuhiko HAGIHARA, Kazuhiko KURATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={25-Gbps/ch Error-Free Operation over 300-m MMF of Low-Power-Consumption Silicon-Photonics-Based Chip-Scale Optical I/O Cores},
year={2016},
volume={E99-C},
number={2},
pages={148-156},
abstract={Aiming to solve the input/output (I/O) bottleneck concerning next-generation interconnections, 5×5-millimeters-squared silicon-photonics-based chip-scale optical transmitters/receivers (TXs/RXs) — called “optical I/O cores” — were developed. In addition to having a compact footprint, by employing low-power-consumption integrated circuits (ICs), as well as providing multimode-fiber (MMF) transmission in the O band and a user-friendly interface, the developed optical I/O cores allow common ease of use with applications such as multi-chip modules (MCMs) and active optical cables (AOCs). The power consumption of their hybrid-integrated ICs is 5mW/Gbps. Their high-density user-friendly optical interface has a spot-size-converter (SSC) function and permits the physical contact against the outer waveguides. As a result, they provide large enough misalignment tolerance to allow use of passive alignment and visual alignment. In a performance test, they demonstrated 25-Gbps/ch error-free operation over 300-m MMF.},
keywords={},
doi={10.1587/transele.E99.C.148},
ISSN={1745-1353},
month={February},}

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TY - JOUR
TI - 25-Gbps/ch Error-Free Operation over 300-m MMF of Low-Power-Consumption Silicon-Photonics-Based Chip-Scale Optical I/O Cores
T2 - IEICE TRANSACTIONS on Electronics
SP - 148
EP - 156
AU - Kenichiro YASHIKI
AU - Toshinori UEMURA
AU - Mitsuru KURIHARA
AU - Yasuyuki SUZUKI
AU - Masatoshi TOKUSHIMA
AU - Yasuhiko HAGIHARA
AU - Kazuhiko KURATA
PY - 2016
DO - 10.1587/transele.E99.C.148
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E99-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2016
AB - Aiming to solve the input/output (I/O) bottleneck concerning next-generation interconnections, 5×5-millimeters-squared silicon-photonics-based chip-scale optical transmitters/receivers (TXs/RXs) — called “optical I/O cores” — were developed. In addition to having a compact footprint, by employing low-power-consumption integrated circuits (ICs), as well as providing multimode-fiber (MMF) transmission in the O band and a user-friendly interface, the developed optical I/O cores allow common ease of use with applications such as multi-chip modules (MCMs) and active optical cables (AOCs). The power consumption of their hybrid-integrated ICs is 5mW/Gbps. Their high-density user-friendly optical interface has a spot-size-converter (SSC) function and permits the physical contact against the outer waveguides. As a result, they provide large enough misalignment tolerance to allow use of passive alignment and visual alignment. In a performance test, they demonstrated 25-Gbps/ch error-free operation over 300-m MMF.
ER -