A fully integrated digital PLL (Phase Locked Loop) with on-chip CMOS oscillator is described. Nominal division number of the variable divider is automatically tuned in this digital PLL and this feature makes it possible to widen the pull-in range. In general, output jitter may increase if the pull-in range is widened. To overcome this problem, output jitter is reduced by utilizing the dual loop architecture. Wide pull-in range enables us on-chip oscillator, which is not so precise as the expensive crystal oscillator. This CMOS oscillator must be carefully designed to be stable against the temperature and the supply voltage variations. Using these digital PLL techniques, together with the on-chip CMOS oscillator, a fully integrated PLL can be achieved. Circuits are designed for 1.544 Mbit/s ISDN primary rate interface, and 6.25% pull-in range is obtained.

A current source with current switches (switched current source) is widely used in various analog ICs. One of its typical application is data converters. This paper describes an analysis of the transient behavior of a switched current source. The analysis has clarified conditions and causes of overshooting in the output waveform. The analysis also clarifies dependence of the settling time on parameters. The waveform heavily depends on time constant and initial charge at the internal node where current source and current switch are connected. They can cause the overshooting and limit the settling time. A phenomenon of acceleration of the settling time and an influence of the charge coupling through current switches are also discussed. A chart mentioned in this paper is useful for the initial design and the improvement of switched current sources.

We have developed a 64-neuron electrically trainable BiCMOS analog neuroprocessor based on 3-layered PDP networks with a feedforward time as short as 10 µs which is equivalent to the operation speed as high as 10⁸ multiplications per second. A crucial point in this development is application of a dynamic refreshment technique to a weighting circuit. A sufficiently long retention time of the synapse weight has thereby been attained, leading to a practical operation of the neuroprocessor.

First, a number of issues pertaining to analog VLSI implementation of Backpropagation (BP) and Deterministic Boltzmann Machine (DBM) learning algorithms are clarified. According to the results from software simulation, a mismatch between the activation function and derivative generated by independent circuits degrades the BP learning performance. The perfomance can be improved, however, by adjusting the gain of the activation function used to obtain the derivative, irrespective of the original activation function. Calculation errors embedded in the circuits also degrade the learning preformance. BP learning is sensitive to offset errors in multiplication in the learning process, and DBM learning is sensitive to asymmetry between the weight increment and decrement processes. Next, an analog VLSI architecture for implementing the algorithms using common building block circuits is proposed. The evaluation results of test chips confirm that synaptic weights can be updated up to 1 MHz and that a resolution exceeding 14 bits can be attained. The test chips successfully perform XOR learning using each algorithm.

This paper describes a new approach towards the performance-driven layout for analog LSIs. Based on our approach, we developed an automatic performance-driven layout system LIBRA. The performance-driven layout has an advantage that numerical evaluations of performance requirements may exactly specify layout requirements so that a better layout result will be expected with regard to both the size and the performances. As the first step to the final goal, we only concern with the DC characteristics of analog circuits affected by the placement and routing. First of all, LIBRA performs the sensitivity analysis with respect to process parameters and wire parasitics, which are major causes for DC performance deviations of analog LSIs, so as to describe every perfomance deviation by its first order approximation. Based on the estimations of those performance deviations, LIBRA designs the placement of devices. The placement approach here is the simulated annealing method driven by their circuit performance specification. The routing of inter-cell wires is performed according to the priority of the larger total wire sensitivities in the net by the maze router. Then, the simple compaction eliminates the empty space as much as possible. After that, the power lines optimization is performed so as to minimize the ferformance deviations. Finally, an advantage of the performance improvement by our approach is demonstrated by showing a layout result of a practical bipolar circuit and its excellent performance evaluations.

A layout system for mixed analog/digital standard cell LSI's is described. The system includes interactive floorplan and placement features and automatic global and channel router. In mixed analog/digital circuits, crosstalk noise causes chip performance degradation. Thus, the proposed global routing algorithm routes analog nets in areas that are free of digital nets as much as possible. The number of line crossovers, especially for analog nets, is minimized by both global and detailed routers, because these crossovers are the dominant factors in the crosstalk noise. Double width lines can be used to avoid unexpected voltage drops caused by parasitic resistances. A postprocess automatically puts up shield lines for very noise sensitive wirings to improve the S/N ratio. Experimental results show that the proposed algorithms are effective in reducing the number of crossovers and redundant vias.

Splice Loss of LP modes in multimode graded-index optical fibers is investigated. It becomes clear that splice loss of particular mode and the excitation rate of the other modes by mode conversion is predicted from the factor, e.g. fiber axis misalignment, fiber and face gap, end fiber end face inclination.

Optical couplers which are composed of three channel waveguides arranged two-dimensionally are investigated numerically. The mode-matching method that matches the boundary conditions in the sense of least squares is applied to this problem, using the hybrid-modal representation. The precise numerical results of the dispersion relations and field distributions are presented for the lowest three modes near the cutoff. The arrangement of three waveguides can be optimized so as to satisfy the condition for maximum power-transfer efficiency.

The authors propose a waveguide π-junction with an inductive post for the element of a multiple-way power divider in a single-layered slotted waveguide array. This π-junction splits part of the power into two branch waveguides through one coupling window, and can excite densely arrayed waveguides at equal phase and amplitude. The power dividing characteristics are analyzed by Galerkin's method of moments and are confirmed experimentally. Reflection from the π-junction is suppressed to the level below 30 dB over 5.4% bandwidth by attaching an inductive post.