Gallium oxide is expected as a channel material for thin film transistors. In the conventional technologies, gallium oxide has been tried to be fabricated by atomic layer deposition (ALD) at high temperatures from 100–450°C, although the room-temperature (RT) growth has not been developed. In this work, we developed the RT ALD of gallium oxide by using a remote plasma technique. We studied trimethylgallium (TMG) adsorption and its oxidization on gallium oxide surfaces at RT by infrared absorption spectroscopy (IRAS). Based on the adsorption and oxidization characteristics, we designed the room temperature ALD of Ga₂O₃. The IRAS indicated that TMG adsorbs on the gallium oxide surface by consuming the adsorption sites of surface hydroxyl groups even at RT and the remote plasma-excited water and oxygen vapor is effective in oxidizing the TMG adsorbed surface and regeneration of the adsorption sites for TMG. We successfully prepared Ga₂O₃ films on Si substrates at RT with a growth per cycle of 0.055 nm/cycle.

Accuracy of a method for analyzing the interface defect properties; time-domain charge pumping method, is evaluated. The method monitors the charge pumping (CP) current in time domain, and thus we expect that it gives us a noble way to investigate the interface state properties. In this study, for the purpose of evaluating the accuracy of the method, the interface state density extracted from the time-domain data is compared with that measured using the conventional CP method. The results show that they are equal to each other for all measured devices with various defect densities, demonstrating that the time-domain CP method is sufficiently accurate for the defect density evaluation.

Nitrogen adsorption on thermally cleaned Si(100) surfaces by pure and plasma excited NH₃ is investigated by in situ IR absorption spectroscopy and ex-situ X-ray photoelectron spectroscopy with various temperatures from RT (25°C) to 800°C and with a treatment time of 5 min. The nitrogen coverage after the treatment varies according to the treatment temperature for both pure and plasma excited NH₃. In case of the pure NH₃, the nitrogen coverage is saturated as low as 0.13–0.25 mono layer (ML) while the growth of the nitride film commenced at 550°C. For the plasma excited NH₃, the saturation coverage was measured at 0.54 ML at RT and it remained unincreased from RT to 550°C. This indicates that the plasma excited NH₃ enhances the nitrogen adsorption near at RT. It is found that main species of N is Si₂= NH in case of the plasma excited NH₃ at RT while the pure NH₃ treatment gives rise to the Si–NH₂ passivation with Si–H at RT. We discuss the mechanism of the nitrogen adsorption on Si(100) surfaces with the plasma excited NH₃ in comparison with the study on the pure NH₃ treatment.

In this study, Si(100) surface flattening process was investigated utilizing sacrificial oxidation method to improve Metal–Insulator–Semiconductor (MIS) diode characteristics. By etching of the 100 nm-thick sacrificial oxide formed by thermal oxidation at 1100°C, the surface roughness of Si substrate was reduced. The obtained Root-Mean-Square (RMS) roughness was decreased from 0.15 nm (as-cleaned) to 0.07 nm in the case of sacrificial oxide formed by wet oxidation, while it was 0.10 nm in the case of dry oxidation. Furthermore, time-dependent dielectric breakdown (TDDB) characteristic of Al/SiO₂(10 nm)/p-Si(100) MIS diode structures was found to be improved by the reduction of Si surface RMS roughness.

Ni nanodots (NDs) used as nano-scale top electrodes were formed on a 10-nm-thick Si-rich oxide (SiO_x)/Ni bottom electrode by exposing a 2-nm-thick Ni layer to remote H₂-plasma (H₂-RP) without external heating, and the resistance-switching behaviors of SiO_x were investigated from current-voltage (I–V) curves. Atomic force microscope (AFM) analyses confirmed the formation of electrically isolated Ni NDs as a result of surface migration and agglomeration of Ni atoms promoted by the surface recombination of H radicals. From local I–V measurements performed by contacting a single Ni ND as a top electrode with a Rh coated Si cantilever, a distinct uni-polar type resistance switching behavior was observed repeatedly despite an average contact area between the Ni ND and the SiO_x as small as ∼ 1.9 × 10^-12cm². This local I–V measurement technique is quite a simple method to evaluate the size scalability of switching properties.

Highly conductive poly(3,4-ethylenedioxythiophene): poly(styrene sulfonate) (PEDOT : PSS) attracts a strong attention as a transparent electrode material since it may replace indium tin oxide (ITO) electrodes used in many organic semiconductor devices. However, PEDOT : PSS films have been usually deposited using acidic precursors, which caused long term device degradation as well as safety issues during device fabrication processes. This paper firstly reports application of highly conductive PEDOT : PSS films deposited on polyethylene terephthalate (PET) substrates using a neutralized precursor to organic bulkhetrojunction solar cells. The sheet resistance (R_s) of PEDOT : PSS was reduced by more than two orders of magnitudes by spin coating the neutralized solution containing 5% of dimethyl sulfoxide (DMSO) and dipping the films in DMSO for 30 min. Subsequently, an approximately 55 nm-thick PEDOT : PSS layer was obtained with R_s =159 Ω/□, a conductivity of 1143 S/m, and an optical transmittance of 84%. A solar cell based on poly[4,8-bis[(2-ethylhexyl)oxy]benzo[1,2-b:4,5-b']dithiophene-2, 6-diyl][3-fluoro-2-[(2-ethylhexyl)carbonyl]thieno[3, 4-b]thiophenediyl]: [6,6]-phenyl-C₇₁-butyric acid methyl ester fabricated on the PEDOT: PSS/PET substrate exhibited a higher open circuit voltage and power conversion efficiency than did a control solar cell fabricated on an ITO-coated PET substrate. These results suggest that the highly conductive PEDOT : PSS films may contribute to realize ITO-free flexible organic solar cells.

We have demonstrated tunable n-channel fullerene and p-channel pentacene OFETs and CMOS inverter circuit based on a bilayer-dielectric structure of CYTOP (poly(perfluoroalkenyl vinyl ether)) electret and SiO₂. For both OFET types, the V_th can be electrically tuned thanks to the charge-trapping at the interface of CYTOP and SiO₂. The stability of the shifted V_th was investigated through monitoring a change in transistor current. The measured transistor current versus time after programming fitted very well with a stretched-exponential distribution with a long time constant up to 10⁶ s. For organic CMOS inverter, after applying the program gate voltages for n-channel fullerene or p-channel pentacene elements, the voltage transfer characteristics were shifted toward more positive values, resulting in a modulation of the noise margin. We realized that at a program gate voltage of 60 V for p-channel OFET, the circuit switched at 4, 8 V, that is close to half supply voltage V_DD, leading to the maximum electrical noise immunity of the inverter circuit.

In this work, resistive switching random-access memory (RRAM) devices having a structure of metal/Si₃N₄/Si with different top electrode metals were fabricated to investigate the changes in switching and conduction mechanisms depending on electrode metals. It is shown that the metal workfunction is not strongly related with either high-resistance state (HRS) and forming voltage. Top electrodes (TEs) of Al, Cu, and Ni show both bipolar and unipolar switching characteristics. The changes of resistances in these devices can be explained by the different defect arrangements in the switching layer (SL). Among the devices with different TE metals, one with Ag electrode does not show unipolar switching unlike the others. The conducting filaments of Ag-electrode device in the low-resistance state (LRS) demonstrated metallic behaviors in the temperature-controlled experiments, which supports that Ag substantially participates in the conduction as a filament source. Moreover, the difference in switching speed is identified depending on TE metals.

We investigate the origin of non-ideal transfer characteristics in graphene-based three-branch nano-junction (TBJ) devices. Fabricated graphene TBJs often show asymmetric nonlinear voltage transfer characteristic, although symmetric one should appear ideally. A simple model considering the contact resistances in two input electrodes is deduced and it suggests that the non-ideal characteristic arises from inequality of the metal-graphene contact resistances in the inputs. We fabricate a graphene TBJ device with electrically equal contacts by optimizing the contact formation process and almost ideal nonlinear characteristic was successfully demonstrated.

Parameter variations in nanometer process technology are one of the major design challenges. They cause delay to be increased on the critical path and may change the logic level of internal nodes. The basic concept to solve these problems at the circuit level, design-for-variability (DFV), is to add an error handling circuit to the conventional circuits so that they are robust to nanometer related variations. The state-of-the-art variation-aware flip flops are mainly evolved from aggressive dynamic voltage and frequency scaling (DVFS) -based low-power application systems which handle errors due to the scaled supply voltage. However, they only detect the timing errors and cannot correct the errors. We propose a variation-aware flip flop which can detect and correct the timing error efficiently. The experimental results show that the proposed variation-aware flip flop is more robust and lower power than the existing approaches.

This paper proposes an ultra-low power fully on-chip CMOS relaxation oscillator (ROSC) for a real-time clock application. The proposed ROSC employs a compensation circuit of a comparator's non-idealities caused by offset voltage and delay time. The ROSC can generate a stable, and 32-kHz oscillation clock frequency without increasing power dissipation by using a low reference voltage and employing a novel compensation architecture for comparators. Measurement results in a 0.18-μm CMOS process demonstrated that the circuit can generate a stable clock frequency of 32.55 kHz with low power dissipation of 472 nW at 1.8-V power supply. Measured line regulation and temperature coefficient were 1.1%/V and 120 ppm/°C, respectively.