Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model

Hidenari NAKASHIMA; Junpei INOUE; Kenichi OKADA; Kazuya MASU

doi:10.1093/ietfec/e88-a.12.3358

Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model

Hidenari NAKASHIMA, Junpei INOUE, Kenichi OKADA, Kazuya MASU

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Interconnect Length Distribution (ILD) represents the correlation between the number of interconnects and their length. The ILD can predict power consumption, clock frequency, chip size, etc. High core utilization and small circuit area have been reported to improve chip performance. We propose an ILD model to predict the correlation between core utilization and chip performance. The proposed model predicts the influences of interconnect length and interconnect density on circuit performances. As core utilization increases, small and simple circuits improve the performances. In large complex circuits, decreasing the wire coupling capacitance is more important than decreasing the total interconnect length for improvement of chip performance. The proposed ILD model expresses the actual ILD more accurately than conventional models.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.12 pp.3358-3366

Publication Date: 2005/12/01

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DOI: 10.1093/ietfec/e88-a.12.3358

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Prediction and Analysis

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Hidenari NAKASHIMA, Junpei INOUE, Kenichi OKADA, Kazuya MASU, "Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model" in IEICE TRANSACTIONS on Fundamentals, vol. E88-A, no. 12, pp. 3358-3366, December 2005, doi: 10.1093/ietfec/e88-a.12.3358.
Abstract: Interconnect Length Distribution (ILD) represents the correlation between the number of interconnects and their length. The ILD can predict power consumption, clock frequency, chip size, etc. High core utilization and small circuit area have been reported to improve chip performance. We propose an ILD model to predict the correlation between core utilization and chip performance. The proposed model predicts the influences of interconnect length and interconnect density on circuit performances. As core utilization increases, small and simple circuits improve the performances. In large complex circuits, decreasing the wire coupling capacitance is more important than decreasing the total interconnect length for improvement of chip performance. The proposed ILD model expresses the actual ILD more accurately than conventional models.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.12.3358/_p

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@ARTICLE{e88-a_12_3358,
author={Hidenari NAKASHIMA, Junpei INOUE, Kenichi OKADA, Kazuya MASU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model},
year={2005},
volume={E88-A},
number={12},
pages={3358-3366},
abstract={Interconnect Length Distribution (ILD) represents the correlation between the number of interconnects and their length. The ILD can predict power consumption, clock frequency, chip size, etc. High core utilization and small circuit area have been reported to improve chip performance. We propose an ILD model to predict the correlation between core utilization and chip performance. The proposed model predicts the influences of interconnect length and interconnect density on circuit performances. As core utilization increases, small and simple circuits improve the performances. In large complex circuits, decreasing the wire coupling capacitance is more important than decreasing the total interconnect length for improvement of chip performance. The proposed ILD model expresses the actual ILD more accurately than conventional models.},
keywords={},
doi={10.1093/ietfec/e88-a.12.3358},
ISSN={},
month={December},}

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TY - JOUR
TI - Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3358
EP - 3366
AU - Hidenari NAKASHIMA
AU - Junpei INOUE
AU - Kenichi OKADA
AU - Kazuya MASU
PY - 2005
DO - 10.1093/ietfec/e88-a.12.3358
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2005
AB - Interconnect Length Distribution (ILD) represents the correlation between the number of interconnects and their length. The ILD can predict power consumption, clock frequency, chip size, etc. High core utilization and small circuit area have been reported to improve chip performance. We propose an ILD model to predict the correlation between core utilization and chip performance. The proposed model predicts the influences of interconnect length and interconnect density on circuit performances. As core utilization increases, small and simple circuits improve the performances. In large complex circuits, decreasing the wire coupling capacitance is more important than decreasing the total interconnect length for improvement of chip performance. The proposed ILD model expresses the actual ILD more accurately than conventional models.
ER -