Design of Ogg Vorbis Decoder System for Embedded Platform

Atsushi KOSAKA; Hiroyuki OKUHATA; Takao ONOYE; Isao SHIRAKAWA

doi:10.1093/ietfec/e88-a.8.2124

Design of Ogg Vorbis Decoder System for Embedded Platform

Atsushi KOSAKA, Hiroyuki OKUHATA, Takao ONOYE, Isao SHIRAKAWA

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This paper describes a design of Ogg Vorbis decoder for embedded platform. Since Ogg Vorbis decoding process incurs high computational complexity, a trivial software-based implementation requires high operation frequency. Thus in our design specific hardware modules are devised for functional blocks, which have higher computational complexity than other blocks in Ogg Vorbis decoding process. Based on computational cost analysis of whole decoding process, IMDCT (Inverse Modified Discrete Cosine Transform) and residue decoding process are detected as the computation-intensive functional blocks. As a result of hardware implementation, 73% improvement in CPU load is achieved by specific hardware modules for IMDCT and residue decoding process.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.8 pp.2124-2130

Publication Date: 2005/08/01

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DOI: 10.1093/ietfec/e88-a.8.2124

Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from the 19th Symposium on Signal Processing)

Category: VLSI Design Technology and CAD

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Atsushi KOSAKA, Hiroyuki OKUHATA, Takao ONOYE, Isao SHIRAKAWA, "Design of Ogg Vorbis Decoder System for Embedded Platform" in IEICE TRANSACTIONS on Fundamentals, vol. E88-A, no. 8, pp. 2124-2130, August 2005, doi: 10.1093/ietfec/e88-a.8.2124.
Abstract: This paper describes a design of Ogg Vorbis decoder for embedded platform. Since Ogg Vorbis decoding process incurs high computational complexity, a trivial software-based implementation requires high operation frequency. Thus in our design specific hardware modules are devised for functional blocks, which have higher computational complexity than other blocks in Ogg Vorbis decoding process. Based on computational cost analysis of whole decoding process, IMDCT (Inverse Modified Discrete Cosine Transform) and residue decoding process are detected as the computation-intensive functional blocks. As a result of hardware implementation, 73% improvement in CPU load is achieved by specific hardware modules for IMDCT and residue decoding process.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.8.2124/_p

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@ARTICLE{e88-a_8_2124,
author={Atsushi KOSAKA, Hiroyuki OKUHATA, Takao ONOYE, Isao SHIRAKAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design of Ogg Vorbis Decoder System for Embedded Platform},
year={2005},
volume={E88-A},
number={8},
pages={2124-2130},
abstract={This paper describes a design of Ogg Vorbis decoder for embedded platform. Since Ogg Vorbis decoding process incurs high computational complexity, a trivial software-based implementation requires high operation frequency. Thus in our design specific hardware modules are devised for functional blocks, which have higher computational complexity than other blocks in Ogg Vorbis decoding process. Based on computational cost analysis of whole decoding process, IMDCT (Inverse Modified Discrete Cosine Transform) and residue decoding process are detected as the computation-intensive functional blocks. As a result of hardware implementation, 73% improvement in CPU load is achieved by specific hardware modules for IMDCT and residue decoding process.},
keywords={},
doi={10.1093/ietfec/e88-a.8.2124},
ISSN={},
month={August},}

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TY - JOUR
TI - Design of Ogg Vorbis Decoder System for Embedded Platform
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2124
EP - 2130
AU - Atsushi KOSAKA
AU - Hiroyuki OKUHATA
AU - Takao ONOYE
AU - Isao SHIRAKAWA
PY - 2005
DO - 10.1093/ietfec/e88-a.8.2124
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2005
AB - This paper describes a design of Ogg Vorbis decoder for embedded platform. Since Ogg Vorbis decoding process incurs high computational complexity, a trivial software-based implementation requires high operation frequency. Thus in our design specific hardware modules are devised for functional blocks, which have higher computational complexity than other blocks in Ogg Vorbis decoding process. Based on computational cost analysis of whole decoding process, IMDCT (Inverse Modified Discrete Cosine Transform) and residue decoding process are detected as the computation-intensive functional blocks. As a result of hardware implementation, 73% improvement in CPU load is achieved by specific hardware modules for IMDCT and residue decoding process.
ER -