This paper describes a design of Ogg Vorbis decoder for embedded platform. Since Ogg Vorbis decoding process incurs high computational complexity, a trivial software-based implementation requires high operation frequency. Thus in our design specific hardware modules are devised for functional blocks, which have higher computational complexity than other blocks in Ogg Vorbis decoding process. Based on computational cost analysis of whole decoding process, IMDCT (Inverse Modified Discrete Cosine Transform) and residue decoding process are detected as the computation-intensive functional blocks. As a result of hardware implementation, 73% improvement in CPU load is achieved by specific hardware modules for IMDCT and residue decoding process.

In recent years, much research interest has developed in image enhancement and haze removal techniques. With increasing demand for real time enhancement and haze removal, the need for efficient architecture incorporating both haze removal and enhancement is necessary. In this paper, we propose an architecture supporting both real-time Retinex-based image enhancement and haze removal, using a single module. Efficiently leveraging the similarity between Retinex-based image enhancement and haze removal algorithms, we have successfully proposed an architecture supporting both using a single module. The implementation results reveal that just 1% logic circuits overhead is required to support Retinex-based image enhancement in single mode and haze removal based on Retinex model. This reduction in computation complexity by using a single module reduces the processing and memory implications especially in mobile consumer electronics, as opposed to implementing them individually using different modules. Furthermore, we utilize image enhancement for transmission map estimation instead of soft matting, thereby avoiding further computation complexity which would affect our goal of realizing high frame-rate real time processing. Our FPGA implementation, operating at an optimum frequency of 125MHz with 5.67M total block memory bit size, supports WUXGA (1,920×1,200) 60fps as well as 1080p60 color input. Our proposed design is competitive with existing state-of-the-art designs. Our proposal is tailored to enhance consumer electronic such as on-board cameras, active surveillance intrusion detection systems, autonomous cars, mobile streaming systems and robotics with low processing and memory requirements.

A VLSI implementation of a low-power DSP core is described, which is dedicated to the G. 723. 1 low bitrate speech codec. A number of sophisticated DSP microarchitectures are devised mainly on dual multiply accumulators, rounding and saturation mechanisms, and two-banked on-chip memory. The main attempt is focused on lowering the clock frequency, and therefore on reducing the total power consumption, at the cost of a fairly small increase of chip area. The proposed DSP architecture has been integrated in the total area of 7. 75 mm2 by using a 0. 35 µm CMOS technology, which can operate at 10 MHz with the dissipation of 44. 9 mW from a single 3 V supply.

In the field of education such as elementary and middle schools, teachers want to take care of schoolchildren during physical trainings and after-school club activities. On the other hand, in the field of sports such as professional and national-level sports, physical or technical trainers want to manage the health, physical and physiological conditions of athletes during exercise trainings in the grounds. In this way, it is required to monitor vital signs for persons during exercises, however, there are several technical problems to be solved in its realization. In this paper, we present the importance and necessity of vital monitoring for persons during exercises, and to make it possible periodically, reliably and in real-time, we present the solutions which we have so far worked out and point out remaining technical challenges in terms of vital/physical sensing, wireless transmission and human interface.

When we collect vital data from exercisers by putting wireless sensor nodes to them, the reliability of the wireless data collection is dependent on the position of node on the body of exerciser, therefore, in order to determine the suitable body position, it is essential to evaluate the data collection performances by changing the body positions of nodes in experiments involving human subjects. However, their fair comparison is problematic, because the experiments have no repeatability, that is, we cannot evaluate the performances for multiple body positions in an experiment at the same time. In this paper, we predict the performances by a software network simulator. Using two main functions such as a channel state function and a mobility function, the network simulator can repeatedly generate the same channel and mobility conditions for nodes. Numerical result obtained by the network simulator shows that when collecting vital data from twenty two footballers in a game, among three body position such as waist, forearm and calf, the forearm position gives the highest data collection rate and the predicted data collection rates agree well with the ones obtained by an experiment involving real subjects.