A Hardware Algorithm for Integer Division Using the SD2 Representation

Naofumi TAKAGI; Shunsuke KADOWAKI; Kazuyoshi TAKAGI

doi:10.1093/ietfec/e89-a.10.2874

A Hardware Algorithm for Integer Division Using the SD2 Representation

Naofumi TAKAGI, Shunsuke KADOWAKI, Kazuyoshi TAKAGI

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A hardware algorithm for integer division is proposed. It is based on the radix-2 non-restoring division algorithm. Fast computation is achieved by the use of the radix-2 signed-digit (SD2) representation. The algorithm does not require normalization of the divisor, and hence, does not require an area-consuming leading-one (or zero) detection nor shifts of variable-amount. Combinational (unfolded) implementation of the algorithm yields a regularly structured array divider, and sequential implementation yields compact dividers.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.10 pp.2874-2881

Publication Date: 2006/10/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e89-a.10.2874

Type of Manuscript: PAPER

Category: VLSI Design Technology and CAD

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Naofumi TAKAGI, Shunsuke KADOWAKI, Kazuyoshi TAKAGI, "A Hardware Algorithm for Integer Division Using the SD2 Representation" in IEICE TRANSACTIONS on Fundamentals, vol. E89-A, no. 10, pp. 2874-2881, October 2006, doi: 10.1093/ietfec/e89-a.10.2874.
Abstract: A hardware algorithm for integer division is proposed. It is based on the radix-2 non-restoring division algorithm. Fast computation is achieved by the use of the radix-2 signed-digit (SD2) representation. The algorithm does not require normalization of the divisor, and hence, does not require an area-consuming leading-one (or zero) detection nor shifts of variable-amount. Combinational (unfolded) implementation of the algorithm yields a regularly structured array divider, and sequential implementation yields compact dividers.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.10.2874/_p

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@ARTICLE{e89-a_10_2874,
author={Naofumi TAKAGI, Shunsuke KADOWAKI, Kazuyoshi TAKAGI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Hardware Algorithm for Integer Division Using the SD2 Representation},
year={2006},
volume={E89-A},
number={10},
pages={2874-2881},
abstract={A hardware algorithm for integer division is proposed. It is based on the radix-2 non-restoring division algorithm. Fast computation is achieved by the use of the radix-2 signed-digit (SD2) representation. The algorithm does not require normalization of the divisor, and hence, does not require an area-consuming leading-one (or zero) detection nor shifts of variable-amount. Combinational (unfolded) implementation of the algorithm yields a regularly structured array divider, and sequential implementation yields compact dividers.},
keywords={},
doi={10.1093/ietfec/e89-a.10.2874},
ISSN={1745-1337},
month={October},}

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TY - JOUR
TI - A Hardware Algorithm for Integer Division Using the SD2 Representation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2874
EP - 2881
AU - Naofumi TAKAGI
AU - Shunsuke KADOWAKI
AU - Kazuyoshi TAKAGI
PY - 2006
DO - 10.1093/ietfec/e89-a.10.2874
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 2006
AB - A hardware algorithm for integer division is proposed. It is based on the radix-2 non-restoring division algorithm. Fast computation is achieved by the use of the radix-2 signed-digit (SD2) representation. The algorithm does not require normalization of the divisor, and hence, does not require an area-consuming leading-one (or zero) detection nor shifts of variable-amount. Combinational (unfolded) implementation of the algorithm yields a regularly structured array divider, and sequential implementation yields compact dividers.
ER -