All Digital Dividing Ratio Changeable PLL Using Delay Clock Pulse with Low Jitter

Mitsutoshi YAHARA; Kuniaki FUJIMOTO; Hirofumi SASAKI; Takashi SHIBUYA; Yoshinori HIGASHI

doi:10.1093/ietfec/e89-a.6.1527

All Digital Dividing Ratio Changeable PLL Using Delay Clock Pulse with Low Jitter

Mitsutoshi YAHARA, Kuniaki FUJIMOTO, Hirofumi SASAKI, Takashi SHIBUYA, Yoshinori HIGASHI

Full Text Views

0

Share
Cite this

Summary :

This paper proposes a new all digital dividing ratio changeable phase locked loop (D-DCPLL) using delay clock pulse that exhibits low output jitter characteristics compared with the conventional DCPLL. This is achieved by employing the delay clock pulse generated from the ring oscillator for the standard clock controlling the loop. This output jitter is always constant regardless of the frequency fluctuation of the delay clock, and the fluctuation coefficient has little effect on the output jitter. This circuit can expand the upper bound frequency of the lock-in range compared with conventional DCPLL when the permissible output jitter is identical. Furthermore, the proposed D-DCPLL can obtain an initial pull-in in one period of the input signal and the multiplication output signal of the constant pulse interval can be obtained by using the remainder control circuit.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.6 pp.1527-1532

Publication Date: 2006/06/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e89-a.6.1527

Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005))

Category

Cite this

Copy

Mitsutoshi YAHARA, Kuniaki FUJIMOTO, Hirofumi SASAKI, Takashi SHIBUYA, Yoshinori HIGASHI, "All Digital Dividing Ratio Changeable PLL Using Delay Clock Pulse with Low Jitter" in IEICE TRANSACTIONS on Fundamentals, vol. E89-A, no. 6, pp. 1527-1532, June 2006, doi: 10.1093/ietfec/e89-a.6.1527.
Abstract: This paper proposes a new all digital dividing ratio changeable phase locked loop (D-DCPLL) using delay clock pulse that exhibits low output jitter characteristics compared with the conventional DCPLL. This is achieved by employing the delay clock pulse generated from the ring oscillator for the standard clock controlling the loop. This output jitter is always constant regardless of the frequency fluctuation of the delay clock, and the fluctuation coefficient has little effect on the output jitter. This circuit can expand the upper bound frequency of the lock-in range compared with conventional DCPLL when the permissible output jitter is identical. Furthermore, the proposed D-DCPLL can obtain an initial pull-in in one period of the input signal and the multiplication output signal of the constant pulse interval can be obtained by using the remainder control circuit.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.6.1527/_p

Copy

@ARTICLE{e89-a_6_1527,
author={Mitsutoshi YAHARA, Kuniaki FUJIMOTO, Hirofumi SASAKI, Takashi SHIBUYA, Yoshinori HIGASHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={All Digital Dividing Ratio Changeable PLL Using Delay Clock Pulse with Low Jitter},
year={2006},
volume={E89-A},
number={6},
pages={1527-1532},
abstract={This paper proposes a new all digital dividing ratio changeable phase locked loop (D-DCPLL) using delay clock pulse that exhibits low output jitter characteristics compared with the conventional DCPLL. This is achieved by employing the delay clock pulse generated from the ring oscillator for the standard clock controlling the loop. This output jitter is always constant regardless of the frequency fluctuation of the delay clock, and the fluctuation coefficient has little effect on the output jitter. This circuit can expand the upper bound frequency of the lock-in range compared with conventional DCPLL when the permissible output jitter is identical. Furthermore, the proposed D-DCPLL can obtain an initial pull-in in one period of the input signal and the multiplication output signal of the constant pulse interval can be obtained by using the remainder control circuit.},
keywords={},
doi={10.1093/ietfec/e89-a.6.1527},
ISSN={1745-1337},
month={June},}

Copy

TY - JOUR
TI - All Digital Dividing Ratio Changeable PLL Using Delay Clock Pulse with Low Jitter
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1527
EP - 1532
AU - Mitsutoshi YAHARA
AU - Kuniaki FUJIMOTO
AU - Hirofumi SASAKI
AU - Takashi SHIBUYA
AU - Yoshinori HIGASHI
PY - 2006
DO - 10.1093/ietfec/e89-a.6.1527
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2006
AB - This paper proposes a new all digital dividing ratio changeable phase locked loop (D-DCPLL) using delay clock pulse that exhibits low output jitter characteristics compared with the conventional DCPLL. This is achieved by employing the delay clock pulse generated from the ring oscillator for the standard clock controlling the loop. This output jitter is always constant regardless of the frequency fluctuation of the delay clock, and the fluctuation coefficient has little effect on the output jitter. This circuit can expand the upper bound frequency of the lock-in range compared with conventional DCPLL when the permissible output jitter is identical. Furthermore, the proposed D-DCPLL can obtain an initial pull-in in one period of the input signal and the multiplication output signal of the constant pulse interval can be obtained by using the remainder control circuit.
ER -