VLSI Design of a Fully-Parallel High-Throughput Decoder for Turbo Gallager Codes

Luca FANUCCI; Pasquale CIAO; Giulio COLAVOLPE

doi:10.1093/ietfec/e89-a.7.1976

VLSI Design of a Fully-Parallel High-Throughput Decoder for Turbo Gallager Codes

Luca FANUCCI, Pasquale CIAO, Giulio COLAVOLPE

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The most powerful channel coding schemes, namely those based on turbo codes and low-density parity-check (LDPC) Gallager codes, have in common the principle of iterative decoding. However, the relative coding structures and decoding algorithms are substantially different. This paper presents a 2048-bit, rate-1/2 soft decision decoder for a new class of codes known as Turbo Gallager Codes. These codes are turbo codes with properly chosen component convolutional codes such that they can be successfully decoded by means of the decoding algorithm used for LDPC codes, i.e., the belief propagation algorithm working on the code Tanner graph. These coding schemes are important in practical terms for two reasons: (i) they can be encoded as classical turbo codes, giving a solution to the encoding problem of LDPC codes; (ii) they can also be decoded in a fully parallel manner, partially overcoming the routing congestion bottleneck of parallel decoder VLSI implementations thanks to the locality of the interconnections. The implemented decoder can support up to 1 Gbit/s data rate and performs up to 48 decoding iterations ensuring both high throughput and good coding gain. In order to evaluate the performance and the gate complexity of the decoder VLSI architecture, it has been synthesized in a 0.18 µm standard-cell CMOS technology.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.7 pp.1976-1986

Publication Date: 2006/07/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e89-a.7.1976

Type of Manuscript: PAPER

Category: Digital Signal Processing

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Luca FANUCCI, Pasquale CIAO, Giulio COLAVOLPE, "VLSI Design of a Fully-Parallel High-Throughput Decoder for Turbo Gallager Codes" in IEICE TRANSACTIONS on Fundamentals, vol. E89-A, no. 7, pp. 1976-1986, July 2006, doi: 10.1093/ietfec/e89-a.7.1976.
Abstract: The most powerful channel coding schemes, namely those based on turbo codes and low-density parity-check (LDPC) Gallager codes, have in common the principle of iterative decoding. However, the relative coding structures and decoding algorithms are substantially different. This paper presents a 2048-bit, rate-1/2 soft decision decoder for a new class of codes known as Turbo Gallager Codes. These codes are turbo codes with properly chosen component convolutional codes such that they can be successfully decoded by means of the decoding algorithm used for LDPC codes, i.e., the belief propagation algorithm working on the code Tanner graph. These coding schemes are important in practical terms for two reasons: (i) they can be encoded as classical turbo codes, giving a solution to the encoding problem of LDPC codes; (ii) they can also be decoded in a fully parallel manner, partially overcoming the routing congestion bottleneck of parallel decoder VLSI implementations thanks to the locality of the interconnections. The implemented decoder can support up to 1 Gbit/s data rate and performs up to 48 decoding iterations ensuring both high throughput and good coding gain. In order to evaluate the performance and the gate complexity of the decoder VLSI architecture, it has been synthesized in a 0.18 µm standard-cell CMOS technology.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.7.1976/_p

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@ARTICLE{e89-a_7_1976,
author={Luca FANUCCI, Pasquale CIAO, Giulio COLAVOLPE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={VLSI Design of a Fully-Parallel High-Throughput Decoder for Turbo Gallager Codes},
year={2006},
volume={E89-A},
number={7},
pages={1976-1986},
abstract={The most powerful channel coding schemes, namely those based on turbo codes and low-density parity-check (LDPC) Gallager codes, have in common the principle of iterative decoding. However, the relative coding structures and decoding algorithms are substantially different. This paper presents a 2048-bit, rate-1/2 soft decision decoder for a new class of codes known as Turbo Gallager Codes. These codes are turbo codes with properly chosen component convolutional codes such that they can be successfully decoded by means of the decoding algorithm used for LDPC codes, i.e., the belief propagation algorithm working on the code Tanner graph. These coding schemes are important in practical terms for two reasons: (i) they can be encoded as classical turbo codes, giving a solution to the encoding problem of LDPC codes; (ii) they can also be decoded in a fully parallel manner, partially overcoming the routing congestion bottleneck of parallel decoder VLSI implementations thanks to the locality of the interconnections. The implemented decoder can support up to 1 Gbit/s data rate and performs up to 48 decoding iterations ensuring both high throughput and good coding gain. In order to evaluate the performance and the gate complexity of the decoder VLSI architecture, it has been synthesized in a 0.18 µm standard-cell CMOS technology.},
keywords={},
doi={10.1093/ietfec/e89-a.7.1976},
ISSN={1745-1337},
month={July},}

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TY - JOUR
TI - VLSI Design of a Fully-Parallel High-Throughput Decoder for Turbo Gallager Codes
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1976
EP - 1986
AU - Luca FANUCCI
AU - Pasquale CIAO
AU - Giulio COLAVOLPE
PY - 2006
DO - 10.1093/ietfec/e89-a.7.1976
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2006
AB - The most powerful channel coding schemes, namely those based on turbo codes and low-density parity-check (LDPC) Gallager codes, have in common the principle of iterative decoding. However, the relative coding structures and decoding algorithms are substantially different. This paper presents a 2048-bit, rate-1/2 soft decision decoder for a new class of codes known as Turbo Gallager Codes. These codes are turbo codes with properly chosen component convolutional codes such that they can be successfully decoded by means of the decoding algorithm used for LDPC codes, i.e., the belief propagation algorithm working on the code Tanner graph. These coding schemes are important in practical terms for two reasons: (i) they can be encoded as classical turbo codes, giving a solution to the encoding problem of LDPC codes; (ii) they can also be decoded in a fully parallel manner, partially overcoming the routing congestion bottleneck of parallel decoder VLSI implementations thanks to the locality of the interconnections. The implemented decoder can support up to 1 Gbit/s data rate and performs up to 48 decoding iterations ensuring both high throughput and good coding gain. In order to evaluate the performance and the gate complexity of the decoder VLSI architecture, it has been synthesized in a 0.18 µm standard-cell CMOS technology.
ER -