Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level

Daisuke SUZUKI; Minoru SAEKI; Tetsuya ICHIKAWA

doi:10.1093/ietfec/e90-a.1.160

Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level

Daisuke SUZUKI, Minoru SAEKI, Tetsuya ICHIKAWA

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This paper proposes a new countermeasure, Random Switching Logic (RSL), against DPA (Differential Power Analysis) and Second-Order DPA at the logic level. RSL makes a signal transition uniform at each gate and suppresses the propagation of glitch to allow power consumption to be independent of predictable data. Furthermore, we implement basic logic circuits on the FPGA (Field Programmable Gate Array) by using RSL, and evaluate the effectiveness. As a result, we confirm the fact that the secure circuit can be structured against DPA and Second-Order DPA.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.1 pp.160-168

Publication Date: 2007/01/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e90-a.1.160

Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security)

Category: Side Channel Attacks

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Daisuke SUZUKI, Minoru SAEKI, Tetsuya ICHIKAWA, "Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level" in IEICE TRANSACTIONS on Fundamentals, vol. E90-A, no. 1, pp. 160-168, January 2007, doi: 10.1093/ietfec/e90-a.1.160.
Abstract: This paper proposes a new countermeasure, Random Switching Logic (RSL), against DPA (Differential Power Analysis) and Second-Order DPA at the logic level. RSL makes a signal transition uniform at each gate and suppresses the propagation of glitch to allow power consumption to be independent of predictable data. Furthermore, we implement basic logic circuits on the FPGA (Field Programmable Gate Array) by using RSL, and evaluate the effectiveness. As a result, we confirm the fact that the secure circuit can be structured against DPA and Second-Order DPA.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.1.160/_p

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@ARTICLE{e90-a_1_160,
author={Daisuke SUZUKI, Minoru SAEKI, Tetsuya ICHIKAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level},
year={2007},
volume={E90-A},
number={1},
pages={160-168},
abstract={This paper proposes a new countermeasure, Random Switching Logic (RSL), against DPA (Differential Power Analysis) and Second-Order DPA at the logic level. RSL makes a signal transition uniform at each gate and suppresses the propagation of glitch to allow power consumption to be independent of predictable data. Furthermore, we implement basic logic circuits on the FPGA (Field Programmable Gate Array) by using RSL, and evaluate the effectiveness. As a result, we confirm the fact that the secure circuit can be structured against DPA and Second-Order DPA.},
keywords={},
doi={10.1093/ietfec/e90-a.1.160},
ISSN={1745-1337},
month={January},}

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TY - JOUR
TI - Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 160
EP - 168
AU - Daisuke SUZUKI
AU - Minoru SAEKI
AU - Tetsuya ICHIKAWA
PY - 2007
DO - 10.1093/ietfec/e90-a.1.160
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2007
AB - This paper proposes a new countermeasure, Random Switching Logic (RSL), against DPA (Differential Power Analysis) and Second-Order DPA at the logic level. RSL makes a signal transition uniform at each gate and suppresses the propagation of glitch to allow power consumption to be independent of predictable data. Furthermore, we implement basic logic circuits on the FPGA (Field Programmable Gate Array) by using RSL, and evaluate the effectiveness. As a result, we confirm the fact that the secure circuit can be structured against DPA and Second-Order DPA.
ER -