Leakage Analysis of DPA Countermeasures at the Logic Level

Minoru SAEKI; Daisuke SUZUKI; Tetsuya ICHIKAWA

doi:10.1093/ietfec/e90-a.1.169

Leakage Analysis of DPA Countermeasures at the Logic Level

Minoru SAEKI, Daisuke SUZUKI, Tetsuya ICHIKAWA

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In this paper, we propose new models for directly evaluating DPA leakage from logic information in CMOS circuits. These models are based on the transition probability for each gate, and are naturally applicable to various actual devices for simulating power analysis. Furthermore, we demonstrate the weakness of previously known hardware countermeasures for both our model and FPGA and suggest secure conditions for the hardware countermeasure.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.1 pp.169-178

Publication Date: 2007/01/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e90-a.1.169

Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security)

Category: Side Channel Attacks

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Minoru SAEKI, Daisuke SUZUKI, Tetsuya ICHIKAWA, "Leakage Analysis of DPA Countermeasures at the Logic Level" in IEICE TRANSACTIONS on Fundamentals, vol. E90-A, no. 1, pp. 169-178, January 2007, doi: 10.1093/ietfec/e90-a.1.169.
Abstract: In this paper, we propose new models for directly evaluating DPA leakage from logic information in CMOS circuits. These models are based on the transition probability for each gate, and are naturally applicable to various actual devices for simulating power analysis. Furthermore, we demonstrate the weakness of previously known hardware countermeasures for both our model and FPGA and suggest secure conditions for the hardware countermeasure.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.1.169/_p

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@ARTICLE{e90-a_1_169,
author={Minoru SAEKI, Daisuke SUZUKI, Tetsuya ICHIKAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Leakage Analysis of DPA Countermeasures at the Logic Level},
year={2007},
volume={E90-A},
number={1},
pages={169-178},
abstract={In this paper, we propose new models for directly evaluating DPA leakage from logic information in CMOS circuits. These models are based on the transition probability for each gate, and are naturally applicable to various actual devices for simulating power analysis. Furthermore, we demonstrate the weakness of previously known hardware countermeasures for both our model and FPGA and suggest secure conditions for the hardware countermeasure.},
keywords={},
doi={10.1093/ietfec/e90-a.1.169},
ISSN={1745-1337},
month={January},}

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TY - JOUR
TI - Leakage Analysis of DPA Countermeasures at the Logic Level
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 169
EP - 178
AU - Minoru SAEKI
AU - Daisuke SUZUKI
AU - Tetsuya ICHIKAWA
PY - 2007
DO - 10.1093/ietfec/e90-a.1.169
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2007
AB - In this paper, we propose new models for directly evaluating DPA leakage from logic information in CMOS circuits. These models are based on the transition probability for each gate, and are naturally applicable to various actual devices for simulating power analysis. Furthermore, we demonstrate the weakness of previously known hardware countermeasures for both our model and FPGA and suggest secure conditions for the hardware countermeasure.
ER -