A High-Performance Architecture of Motion Adaptive De-interlacing with Reliable Interfield Information

Chung-chi LIN; Ming-hwa SHEU; Huann-keng CHIANG; Chih-Jen WEI; Chishyan LIAW

doi:10.1093/ietfec/e90-a.11.2575

A High-Performance Architecture of Motion Adaptive De-interlacing with Reliable Interfield Information

Chung-chi LIN, Ming-hwa SHEU, Huann-keng CHIANG, Chih-Jen WEI, Chishyan LIAW

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Scene changes occur frequently in film broadcasting, and tend to destabilize the performance with blurred, jagged, and artifacts effects when de-interlacing methods are utilized. This paper presents an efficient VLSI architecture of video de-interlacing with considering scene change to improve the quality of video results. This de-interlacing architecture contains three main parts. The first is scene change detection, which is designed based on examining the absolute pixel difference value of two adjacent even or odd fields. The second is background index mechanism for classifying motion and non-motion pixels of input field. The third component, spatial-temporal edge-based median filter, is used to deal with the interpolation for those motion pixels. Comparing with the existed de-interlacing approaches, our architecture design can significantly ameliorate the PSNRs of the video sequences with various scene changes; for other situations, it also maintains better performances. The proposed architecture has been implemented as a VLSI chip based on UMC 0.18-µm CMOS technology process. The total gate count is 30114 and its layout area is about 710 710-µm. The power consumption is 39.78 mW at working frequency 128.2 MHz, which is able to process de-interlacing for HDTV in real-time.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.11 pp.2575-2583

Publication Date: 2007/11/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e90-a.11.2575

Type of Manuscript: PAPER

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Chung-chi LIN, Ming-hwa SHEU, Huann-keng CHIANG, Chih-Jen WEI, Chishyan LIAW, "A High-Performance Architecture of Motion Adaptive De-interlacing with Reliable Interfield Information" in IEICE TRANSACTIONS on Fundamentals, vol. E90-A, no. 11, pp. 2575-2583, November 2007, doi: 10.1093/ietfec/e90-a.11.2575.
Abstract: Scene changes occur frequently in film broadcasting, and tend to destabilize the performance with blurred, jagged, and artifacts effects when de-interlacing methods are utilized. This paper presents an efficient VLSI architecture of video de-interlacing with considering scene change to improve the quality of video results. This de-interlacing architecture contains three main parts. The first is scene change detection, which is designed based on examining the absolute pixel difference value of two adjacent even or odd fields. The second is background index mechanism for classifying motion and non-motion pixels of input field. The third component, spatial-temporal edge-based median filter, is used to deal with the interpolation for those motion pixels. Comparing with the existed de-interlacing approaches, our architecture design can significantly ameliorate the PSNRs of the video sequences with various scene changes; for other situations, it also maintains better performances. The proposed architecture has been implemented as a VLSI chip based on UMC 0.18-µm CMOS technology process. The total gate count is 30114 and its layout area is about 710 710-µm. The power consumption is 39.78 mW at working frequency 128.2 MHz, which is able to process de-interlacing for HDTV in real-time.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.11.2575/_p

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@ARTICLE{e90-a_11_2575,
author={Chung-chi LIN, Ming-hwa SHEU, Huann-keng CHIANG, Chih-Jen WEI, Chishyan LIAW, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A High-Performance Architecture of Motion Adaptive De-interlacing with Reliable Interfield Information},
year={2007},
volume={E90-A},
number={11},
pages={2575-2583},
abstract={Scene changes occur frequently in film broadcasting, and tend to destabilize the performance with blurred, jagged, and artifacts effects when de-interlacing methods are utilized. This paper presents an efficient VLSI architecture of video de-interlacing with considering scene change to improve the quality of video results. This de-interlacing architecture contains three main parts. The first is scene change detection, which is designed based on examining the absolute pixel difference value of two adjacent even or odd fields. The second is background index mechanism for classifying motion and non-motion pixels of input field. The third component, spatial-temporal edge-based median filter, is used to deal with the interpolation for those motion pixels. Comparing with the existed de-interlacing approaches, our architecture design can significantly ameliorate the PSNRs of the video sequences with various scene changes; for other situations, it also maintains better performances. The proposed architecture has been implemented as a VLSI chip based on UMC 0.18-µm CMOS technology process. The total gate count is 30114 and its layout area is about 710 710-µm. The power consumption is 39.78 mW at working frequency 128.2 MHz, which is able to process de-interlacing for HDTV in real-time.},
keywords={},
doi={10.1093/ietfec/e90-a.11.2575},
ISSN={1745-1337},
month={November},}

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TY - JOUR
TI - A High-Performance Architecture of Motion Adaptive De-interlacing with Reliable Interfield Information
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2575
EP - 2583
AU - Chung-chi LIN
AU - Ming-hwa SHEU
AU - Huann-keng CHIANG
AU - Chih-Jen WEI
AU - Chishyan LIAW
PY - 2007
DO - 10.1093/ietfec/e90-a.11.2575
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2007
AB - Scene changes occur frequently in film broadcasting, and tend to destabilize the performance with blurred, jagged, and artifacts effects when de-interlacing methods are utilized. This paper presents an efficient VLSI architecture of video de-interlacing with considering scene change to improve the quality of video results. This de-interlacing architecture contains three main parts. The first is scene change detection, which is designed based on examining the absolute pixel difference value of two adjacent even or odd fields. The second is background index mechanism for classifying motion and non-motion pixels of input field. The third component, spatial-temporal edge-based median filter, is used to deal with the interpolation for those motion pixels. Comparing with the existed de-interlacing approaches, our architecture design can significantly ameliorate the PSNRs of the video sequences with various scene changes; for other situations, it also maintains better performances. The proposed architecture has been implemented as a VLSI chip based on UMC 0.18-µm CMOS technology process. The total gate count is 30114 and its layout area is about 710 710-µm. The power consumption is 39.78 mW at working frequency 128.2 MHz, which is able to process de-interlacing for HDTV in real-time.
ER -