An Algorithm to Improve the Performance of M-Channel Time-Interleaved A-D Converters

Koji ASAMI

doi:10.1093/ietfec/e90-a.12.2846

An Algorithm to Improve the Performance of M-Channel Time-Interleaved A-D Converters

Koji ASAMI

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One method for achieving high-speed waveform digitizing uses time-interleaved A-D Converters (ADCs). It is known that, in this method, using multiple ADCs enables sampling at a rate higher than the sampling rate of the ADC being used. Degradation of the dynamic range, however, results from such factors as phase error in the sampling clock applied to the ADC, and mismatched frequency characteristics among the individual ADCs. This paper describes a method for correcting these mismatches using a digital signal processing (DSP) technique. This method can be applied to any number of interleaved ADCs, and it does not require any additional hardware; good correction and improved accuracy can be obtained simply by adding a little to the computing overhead.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.12 pp.2846-2852

Publication Date: 2007/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e90-a.12.2846

Type of Manuscript: PAPER

Category: Analog Signal Processing

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Koji ASAMI, "An Algorithm to Improve the Performance of M-Channel Time-Interleaved A-D Converters" in IEICE TRANSACTIONS on Fundamentals, vol. E90-A, no. 12, pp. 2846-2852, December 2007, doi: 10.1093/ietfec/e90-a.12.2846.
Abstract: One method for achieving high-speed waveform digitizing uses time-interleaved A-D Converters (ADCs). It is known that, in this method, using multiple ADCs enables sampling at a rate higher than the sampling rate of the ADC being used. Degradation of the dynamic range, however, results from such factors as phase error in the sampling clock applied to the ADC, and mismatched frequency characteristics among the individual ADCs. This paper describes a method for correcting these mismatches using a digital signal processing (DSP) technique. This method can be applied to any number of interleaved ADCs, and it does not require any additional hardware; good correction and improved accuracy can be obtained simply by adding a little to the computing overhead.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.12.2846/_p

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@ARTICLE{e90-a_12_2846,
author={Koji ASAMI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Algorithm to Improve the Performance of M-Channel Time-Interleaved A-D Converters},
year={2007},
volume={E90-A},
number={12},
pages={2846-2852},
abstract={One method for achieving high-speed waveform digitizing uses time-interleaved A-D Converters (ADCs). It is known that, in this method, using multiple ADCs enables sampling at a rate higher than the sampling rate of the ADC being used. Degradation of the dynamic range, however, results from such factors as phase error in the sampling clock applied to the ADC, and mismatched frequency characteristics among the individual ADCs. This paper describes a method for correcting these mismatches using a digital signal processing (DSP) technique. This method can be applied to any number of interleaved ADCs, and it does not require any additional hardware; good correction and improved accuracy can be obtained simply by adding a little to the computing overhead.},
keywords={},
doi={10.1093/ietfec/e90-a.12.2846},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - An Algorithm to Improve the Performance of M-Channel Time-Interleaved A-D Converters
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2846
EP - 2852
AU - Koji ASAMI
PY - 2007
DO - 10.1093/ietfec/e90-a.12.2846
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2007
AB - One method for achieving high-speed waveform digitizing uses time-interleaved A-D Converters (ADCs). It is known that, in this method, using multiple ADCs enables sampling at a rate higher than the sampling rate of the ADC being used. Degradation of the dynamic range, however, results from such factors as phase error in the sampling clock applied to the ADC, and mismatched frequency characteristics among the individual ADCs. This paper describes a method for correcting these mismatches using a digital signal processing (DSP) technique. This method can be applied to any number of interleaved ADCs, and it does not require any additional hardware; good correction and improved accuracy can be obtained simply by adding a little to the computing overhead.
ER -