A 10-bit 800-Column Low-Power RAM Bank Including Energy-Efficient D-Flip-Flops for a Column-Parallel ADC

Shunsuke OKURA; Tetsuro OKURA; Bogoda A. INDIKA U.K.; Kenji TANIGUCHI

doi:10.1093/ietfec/e90-a.2.358

A 10-bit 800-Column Low-Power RAM Bank Including Energy-Efficient D-Flip-Flops for a Column-Parallel ADC

Shunsuke OKURA, Tetsuro OKURA, Bogoda A. INDIKA U.K., Kenji TANIGUCHI

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This paper describes the design of a random access memory (RAM) bank with a 0.35-µm CMOS process for column-parallel analog/digital converters (ADC) utilized in CMOS imagers. A dynamic latch is utilized that expends neither input DC nor drain current during the monitoring phase. Accuracy analysis of analog/digital conversion error in the RAM bank is discussed to ensure low power consumption of a counter buffer circuit. Moreover, the counter buffer utilizes a combination of NMOS and CMOS buffers to reduce power consumption. Total power consumption of a 10-bit 800-column 40 MHz RAM bank is 2.9 mA for use in an imager.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.2 pp.358-364

Publication Date: 2007/02/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e90-a.2.358

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)

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Shunsuke OKURA, Tetsuro OKURA, Bogoda A. INDIKA U.K., Kenji TANIGUCHI, "A 10-bit 800-Column Low-Power RAM Bank Including Energy-Efficient D-Flip-Flops for a Column-Parallel ADC" in IEICE TRANSACTIONS on Fundamentals, vol. E90-A, no. 2, pp. 358-364, February 2007, doi: 10.1093/ietfec/e90-a.2.358.
Abstract: This paper describes the design of a random access memory (RAM) bank with a 0.35-µm CMOS process for column-parallel analog/digital converters (ADC) utilized in CMOS imagers. A dynamic latch is utilized that expends neither input DC nor drain current during the monitoring phase. Accuracy analysis of analog/digital conversion error in the RAM bank is discussed to ensure low power consumption of a counter buffer circuit. Moreover, the counter buffer utilizes a combination of NMOS and CMOS buffers to reduce power consumption. Total power consumption of a 10-bit 800-column 40 MHz RAM bank is 2.9 mA for use in an imager.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.2.358/_p

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@ARTICLE{e90-a_2_358,
author={Shunsuke OKURA, Tetsuro OKURA, Bogoda A. INDIKA U.K., Kenji TANIGUCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 10-bit 800-Column Low-Power RAM Bank Including Energy-Efficient D-Flip-Flops for a Column-Parallel ADC},
year={2007},
volume={E90-A},
number={2},
pages={358-364},
abstract={This paper describes the design of a random access memory (RAM) bank with a 0.35-µm CMOS process for column-parallel analog/digital converters (ADC) utilized in CMOS imagers. A dynamic latch is utilized that expends neither input DC nor drain current during the monitoring phase. Accuracy analysis of analog/digital conversion error in the RAM bank is discussed to ensure low power consumption of a counter buffer circuit. Moreover, the counter buffer utilizes a combination of NMOS and CMOS buffers to reduce power consumption. Total power consumption of a 10-bit 800-column 40 MHz RAM bank is 2.9 mA for use in an imager.},
keywords={},
doi={10.1093/ietfec/e90-a.2.358},
ISSN={1745-1337},
month={February},}

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TY - JOUR
TI - A 10-bit 800-Column Low-Power RAM Bank Including Energy-Efficient D-Flip-Flops for a Column-Parallel ADC
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 358
EP - 364
AU - Shunsuke OKURA
AU - Tetsuro OKURA
AU - Bogoda A. INDIKA U.K.
AU - Kenji TANIGUCHI
PY - 2007
DO - 10.1093/ietfec/e90-a.2.358
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2007
AB - This paper describes the design of a random access memory (RAM) bank with a 0.35-µm CMOS process for column-parallel analog/digital converters (ADC) utilized in CMOS imagers. A dynamic latch is utilized that expends neither input DC nor drain current during the monitoring phase. Accuracy analysis of analog/digital conversion error in the RAM bank is discussed to ensure low power consumption of a counter buffer circuit. Moreover, the counter buffer utilizes a combination of NMOS and CMOS buffers to reduce power consumption. Total power consumption of a 10-bit 800-column 40 MHz RAM bank is 2.9 mA for use in an imager.
ER -