An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style

Daisuke SUZUKI; Minoru SAEKI

doi:10.1093/ietfec/e91-a.1.184

An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style

Daisuke SUZUKI, Minoru SAEKI

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In recent years, certain countermeasures against differential power analysis (DPA) at the logic level have been proposed. Recently, Popp and Mangard proposed a new countermeasure-masked dual-rail pre-charge logic (MDPL); this countermeasure combines dual-rail circuits with random masking to improve the wave dynamic differential logic (WDDL). They claimed that it could implement secure circuits using a standard CMOS cell library without special constraints for the place-and-route method because the difference between the loading capacitances of all the pairs of complementary logic gates in MDPL can be compensated for by the random masking. In this paper, we particularly focus on the signal transition of MDPL gates and evaluate the DPA-resistance of MDPL in detail. Our evaluation results reveal that when the input signals have different delay times, leakage occurs in the MDPL as well as WDDL gates, even if MDPL is effective in reducing the leakage caused by the difference in loading capacitances. Furthermore, in order to validate our evaluation, we demonstrate a problem with different input signal delays by conducting measurements for an FPGA.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.1 pp.184-192

Publication Date: 2008/01/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e91-a.1.184

Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security)

Category: Side Channel Attacks

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Daisuke SUZUKI, Minoru SAEKI, "An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style" in IEICE TRANSACTIONS on Fundamentals, vol. E91-A, no. 1, pp. 184-192, January 2008, doi: 10.1093/ietfec/e91-a.1.184.
Abstract: In recent years, certain countermeasures against differential power analysis (DPA) at the logic level have been proposed. Recently, Popp and Mangard proposed a new countermeasure-masked dual-rail pre-charge logic (MDPL); this countermeasure combines dual-rail circuits with random masking to improve the wave dynamic differential logic (WDDL). They claimed that it could implement secure circuits using a standard CMOS cell library without special constraints for the place-and-route method because the difference between the loading capacitances of all the pairs of complementary logic gates in MDPL can be compensated for by the random masking. In this paper, we particularly focus on the signal transition of MDPL gates and evaluate the DPA-resistance of MDPL in detail. Our evaluation results reveal that when the input signals have different delay times, leakage occurs in the MDPL as well as WDDL gates, even if MDPL is effective in reducing the leakage caused by the difference in loading capacitances. Furthermore, in order to validate our evaluation, we demonstrate a problem with different input signal delays by conducting measurements for an FPGA.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.1.184/_p

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@ARTICLE{e91-a_1_184,
author={Daisuke SUZUKI, Minoru SAEKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style},
year={2008},
volume={E91-A},
number={1},
pages={184-192},
abstract={In recent years, certain countermeasures against differential power analysis (DPA) at the logic level have been proposed. Recently, Popp and Mangard proposed a new countermeasure-masked dual-rail pre-charge logic (MDPL); this countermeasure combines dual-rail circuits with random masking to improve the wave dynamic differential logic (WDDL). They claimed that it could implement secure circuits using a standard CMOS cell library without special constraints for the place-and-route method because the difference between the loading capacitances of all the pairs of complementary logic gates in MDPL can be compensated for by the random masking. In this paper, we particularly focus on the signal transition of MDPL gates and evaluate the DPA-resistance of MDPL in detail. Our evaluation results reveal that when the input signals have different delay times, leakage occurs in the MDPL as well as WDDL gates, even if MDPL is effective in reducing the leakage caused by the difference in loading capacitances. Furthermore, in order to validate our evaluation, we demonstrate a problem with different input signal delays by conducting measurements for an FPGA.},
keywords={},
doi={10.1093/ietfec/e91-a.1.184},
ISSN={1745-1337},
month={January},}

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TY - JOUR
TI - An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 184
EP - 192
AU - Daisuke SUZUKI
AU - Minoru SAEKI
PY - 2008
DO - 10.1093/ietfec/e91-a.1.184
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2008
AB - In recent years, certain countermeasures against differential power analysis (DPA) at the logic level have been proposed. Recently, Popp and Mangard proposed a new countermeasure-masked dual-rail pre-charge logic (MDPL); this countermeasure combines dual-rail circuits with random masking to improve the wave dynamic differential logic (WDDL). They claimed that it could implement secure circuits using a standard CMOS cell library without special constraints for the place-and-route method because the difference between the loading capacitances of all the pairs of complementary logic gates in MDPL can be compensated for by the random masking. In this paper, we particularly focus on the signal transition of MDPL gates and evaluate the DPA-resistance of MDPL in detail. Our evaluation results reveal that when the input signals have different delay times, leakage occurs in the MDPL as well as WDDL gates, even if MDPL is effective in reducing the leakage caused by the difference in loading capacitances. Furthermore, in order to validate our evaluation, we demonstrate a problem with different input signal delays by conducting measurements for an FPGA.
ER -