Research Topics and Results on Simulation for VLSI

Isao SHIRAKAWA; Nagisa ISHIURA

Research Topics and Results on Simulation for VLSI

Isao SHIRAKAWA, Nagisa ISHIURA

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The design of complex VLSI systems relies more and more heavily on scientific computing for numerical simulation and configuration/performance optimization. Especially, computer simulation is becoming a component of VLSI design methodology, for which a variety of computation evolutions have been accomplished for the past two decades. There are many different forms of simulation which are used for verification of VLSI design at various stages of the whole design process. They may be classified into functional or behavioral simulators, register transfer level (RTL) simulators, gate-level logic, or simply logic, simulators, timing simulator, circuit simulators, device simulator, and process simulators. Among these simulation tasks, a series of logic, timing, and circuit simulation is most strongly related to the design stage which deals with logic/electric waveform performance of VLSI circuits. This article surveys the state of the art of VLSI simulation, putting stress mainly on the domain of logic, timing, and circuit simulation, since the reader of the Transactions may be interested exclusively in this field.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E76-A No.7 pp.1070-1076

Publication Date: 1993/07/25

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Type of Manuscript: Special Section PAPER (Special Section on Surveys of Researches in CAS Fields in the Last Two Decades, I)

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Isao SHIRAKAWA, Nagisa ISHIURA, "Research Topics and Results on Simulation for VLSI" in IEICE TRANSACTIONS on Fundamentals, vol. E76-A, no. 7, pp. 1070-1076, July 1993, doi: .
Abstract: The design of complex VLSI systems relies more and more heavily on scientific computing for numerical simulation and configuration/performance optimization. Especially, computer simulation is becoming a component of VLSI design methodology, for which a variety of computation evolutions have been accomplished for the past two decades. There are many different forms of simulation which are used for verification of VLSI design at various stages of the whole design process. They may be classified into functional or behavioral simulators, register transfer level (RTL) simulators, gate-level logic, or simply logic, simulators, timing simulator, circuit simulators, device simulator, and process simulators. Among these simulation tasks, a series of logic, timing, and circuit simulation is most strongly related to the design stage which deals with logic/electric waveform performance of VLSI circuits. This article surveys the state of the art of VLSI simulation, putting stress mainly on the domain of logic, timing, and circuit simulation, since the reader of the Transactions may be interested exclusively in this field.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e76-a_7_1070/_p

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@ARTICLE{e76-a_7_1070,
author={Isao SHIRAKAWA, Nagisa ISHIURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Research Topics and Results on Simulation for VLSI},
year={1993},
volume={E76-A},
number={7},
pages={1070-1076},
abstract={The design of complex VLSI systems relies more and more heavily on scientific computing for numerical simulation and configuration/performance optimization. Especially, computer simulation is becoming a component of VLSI design methodology, for which a variety of computation evolutions have been accomplished for the past two decades. There are many different forms of simulation which are used for verification of VLSI design at various stages of the whole design process. They may be classified into functional or behavioral simulators, register transfer level (RTL) simulators, gate-level logic, or simply logic, simulators, timing simulator, circuit simulators, device simulator, and process simulators. Among these simulation tasks, a series of logic, timing, and circuit simulation is most strongly related to the design stage which deals with logic/electric waveform performance of VLSI circuits. This article surveys the state of the art of VLSI simulation, putting stress mainly on the domain of logic, timing, and circuit simulation, since the reader of the Transactions may be interested exclusively in this field.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - Research Topics and Results on Simulation for VLSI
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1070
EP - 1076
AU - Isao SHIRAKAWA
AU - Nagisa ISHIURA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E76-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 1993
AB - The design of complex VLSI systems relies more and more heavily on scientific computing for numerical simulation and configuration/performance optimization. Especially, computer simulation is becoming a component of VLSI design methodology, for which a variety of computation evolutions have been accomplished for the past two decades. There are many different forms of simulation which are used for verification of VLSI design at various stages of the whole design process. They may be classified into functional or behavioral simulators, register transfer level (RTL) simulators, gate-level logic, or simply logic, simulators, timing simulator, circuit simulators, device simulator, and process simulators. Among these simulation tasks, a series of logic, timing, and circuit simulation is most strongly related to the design stage which deals with logic/electric waveform performance of VLSI circuits. This article surveys the state of the art of VLSI simulation, putting stress mainly on the domain of logic, timing, and circuit simulation, since the reader of the Transactions may be interested exclusively in this field.
ER -