A Global Router Optimizing Timing and Area for High-Speed Bipolar LSIs

Ikuo HARADA; Yuichiro TAKEI; Hitoshi KITAZAWA

A Global Router Optimizing Timing and Area for High-Speed Bipolar LSIs

Ikuo HARADA, Yuichiro TAKEI, Hitoshi KITAZAWA

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A timing-driven global routing algorithm is proposed that directly models the path-based timing constraints. By keeping track of the critical path delay and channel densities, and using novel heuristic criteria, it can select routing paths that minimize area as well as satisfy the timing constraints. Using bipolar-specific features, this router can be used to design LSI chips that handle signals with speeds greater that a gigabit per second. Experimental results shows an average delay improvement of 17.6%.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E77-A No.12 pp.2058-2066

Publication Date: 1994/12/25

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Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

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Ikuo HARADA, Yuichiro TAKEI, Hitoshi KITAZAWA, "A Global Router Optimizing Timing and Area for High-Speed Bipolar LSIs" in IEICE TRANSACTIONS on Fundamentals, vol. E77-A, no. 12, pp. 2058-2066, December 1994, doi: .
Abstract: A timing-driven global routing algorithm is proposed that directly models the path-based timing constraints. By keeping track of the critical path delay and channel densities, and using novel heuristic criteria, it can select routing paths that minimize area as well as satisfy the timing constraints. Using bipolar-specific features, this router can be used to design LSI chips that handle signals with speeds greater that a gigabit per second. Experimental results shows an average delay improvement of 17.6%.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e77-a_12_2058/_p

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@ARTICLE{e77-a_12_2058,
author={Ikuo HARADA, Yuichiro TAKEI, Hitoshi KITAZAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Global Router Optimizing Timing and Area for High-Speed Bipolar LSIs},
year={1994},
volume={E77-A},
number={12},
pages={2058-2066},
abstract={A timing-driven global routing algorithm is proposed that directly models the path-based timing constraints. By keeping track of the critical path delay and channel densities, and using novel heuristic criteria, it can select routing paths that minimize area as well as satisfy the timing constraints. Using bipolar-specific features, this router can be used to design LSI chips that handle signals with speeds greater that a gigabit per second. Experimental results shows an average delay improvement of 17.6%.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - A Global Router Optimizing Timing and Area for High-Speed Bipolar LSIs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2058
EP - 2066
AU - Ikuo HARADA
AU - Yuichiro TAKEI
AU - Hitoshi KITAZAWA
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E77-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1994
AB - A timing-driven global routing algorithm is proposed that directly models the path-based timing constraints. By keeping track of the critical path delay and channel densities, and using novel heuristic criteria, it can select routing paths that minimize area as well as satisfy the timing constraints. Using bipolar-specific features, this router can be used to design LSI chips that handle signals with speeds greater that a gigabit per second. Experimental results shows an average delay improvement of 17.6%.
ER -