We have developed the Epi-Base SATURN process as a silicon bipolar process technology which can be applied to optical transmission LSIs. This process technology, to which low temperature selective epitaxial growth technology is applied, is based on the SATURN process. By performing selective epitaxial growth for base formation in 2 steps, transistors with a 40GHz maximum cut-off frequency have been fabricated. In circuit simulation based on SPICE parameters of transistors, the target performance required for 2.4 Gbit/s optical interface LSIs has been achieved.

A timing-driven global routing algorithm is proposed that directly models the path-based timing constraints. By keeping track of the critical path delay and channel densities, and using novel heuristic criteria, it can select routing paths that minimize area as well as satisfy the timing constraints. Using bipolar-specific features, this router can be used to design LSI chips that handle signals with speeds greater that a gigabit per second. Experimental results shows an average delay improvement of 17.6%.

Junction leakage current of trench isolation devices is strongly influenced by trench configuration. The origin of the leakage current is the mechanical stress that is generated by the differential thermal expansion between the Si substrate and the SiO2 filled isolation trench during the isolation forming process. A two-dimensional mechanical stress simulation was used to analyze trench-isolated devices. The simulated distribution and magnitude of stress were found to agree with Raman spectroscopic measurements of actual devices. The stress in the deeper regions between deep trenches is likely to increase greatly as the size of devices diminishes, so it is important to reduce this stress and thus suppress junction leakage current.

Novel circuit design techniques for bipolar and MOS four-quadrant analog multipliers operable on low supply voltage are described. There are three design techniques for multipliers operable on low supply voltage. One is the transistor-size unbalance technique. Another is the bias offset technique. A third is the multitail technique. Bipolar and MOS four-quadrant analog multipliers proposed in this paper consist of transistor-pairs with different transistor sizes (i.e. emitter areas or gate W/L values are different), transistor-pairs with the same bias offset or multitail cells (i.e. quadritail cells and an octotail cell). Several kinds of squaring circuits consisting of such transistor-pairs are applied to the multipliers when the multiplication method is based on the quarter-square technique. These multipliers all have satisfiable multiplication characteristics with four-quadrant operations in analog signal processing, whether implemented in bipolar technology or implemented in MOS technology.