A Concept of Analog-Digital Merged Circuit Architecture for Future VLSI's

Atsushi IWATA; Makoto NAGATA

A Concept of Analog-Digital Merged Circuit Architecture for Future VLSI's

Atsushi IWATA, Makoto NAGATA

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This paper describes the new analog-digital merged circuit architecture which utilizes the pulse modulation signals. By reconsidering the information representing and processing principles, and the circuit operations governed by the physical law, the new circuit architecture is proposed to overcome the limitations of existent VLSI technologies. The proposed architecture utilizes the pulse width modulation (PWM) signal which has analog information in the time domain, and be constructed with the novel PWM circuits which carry out the multi-input arithmetic operations, the signal conversions and the data storage. It has a potential to exploit the high speed switching capability of deep sub-µm devices, and to reduce the number of devices and the power dissipation to one-tenth of those of the binary digital circuits. Therefore it will effectively implement the intelligent processing systems utilizing 0.5-0.2µm scaled CMOS devices.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E79-A No.2 pp.145-157

Publication Date: 1996/02/25

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Type of Manuscript: Special Section PAPER (Special Section on Analog Technologies in Submicron Era)

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Atsushi IWATA, Makoto NAGATA, "A Concept of Analog-Digital Merged Circuit Architecture for Future VLSI's" in IEICE TRANSACTIONS on Fundamentals, vol. E79-A, no. 2, pp. 145-157, February 1996, doi: .
Abstract: This paper describes the new analog-digital merged circuit architecture which utilizes the pulse modulation signals. By reconsidering the information representing and processing principles, and the circuit operations governed by the physical law, the new circuit architecture is proposed to overcome the limitations of existent VLSI technologies. The proposed architecture utilizes the pulse width modulation (PWM) signal which has analog information in the time domain, and be constructed with the novel PWM circuits which carry out the multi-input arithmetic operations, the signal conversions and the data storage. It has a potential to exploit the high speed switching capability of deep sub-µm devices, and to reduce the number of devices and the power dissipation to one-tenth of those of the binary digital circuits. Therefore it will effectively implement the intelligent processing systems utilizing 0.5-0.2µm scaled CMOS devices.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e79-a_2_145/_p

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@ARTICLE{e79-a_2_145,
author={Atsushi IWATA, Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Concept of Analog-Digital Merged Circuit Architecture for Future VLSI's},
year={1996},
volume={E79-A},
number={2},
pages={145-157},
abstract={This paper describes the new analog-digital merged circuit architecture which utilizes the pulse modulation signals. By reconsidering the information representing and processing principles, and the circuit operations governed by the physical law, the new circuit architecture is proposed to overcome the limitations of existent VLSI technologies. The proposed architecture utilizes the pulse width modulation (PWM) signal which has analog information in the time domain, and be constructed with the novel PWM circuits which carry out the multi-input arithmetic operations, the signal conversions and the data storage. It has a potential to exploit the high speed switching capability of deep sub-µm devices, and to reduce the number of devices and the power dissipation to one-tenth of those of the binary digital circuits. Therefore it will effectively implement the intelligent processing systems utilizing 0.5-0.2µm scaled CMOS devices.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - A Concept of Analog-Digital Merged Circuit Architecture for Future VLSI's
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 145
EP - 157
AU - Atsushi IWATA
AU - Makoto NAGATA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E79-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 1996
AB - This paper describes the new analog-digital merged circuit architecture which utilizes the pulse modulation signals. By reconsidering the information representing and processing principles, and the circuit operations governed by the physical law, the new circuit architecture is proposed to overcome the limitations of existent VLSI technologies. The proposed architecture utilizes the pulse width modulation (PWM) signal which has analog information in the time domain, and be constructed with the novel PWM circuits which carry out the multi-input arithmetic operations, the signal conversions and the data storage. It has a potential to exploit the high speed switching capability of deep sub-µm devices, and to reduce the number of devices and the power dissipation to one-tenth of those of the binary digital circuits. Therefore it will effectively implement the intelligent processing systems utilizing 0.5-0.2µm scaled CMOS devices.
ER -