Ultra-Low Power Two-MOS Virtual-Short Circuit and Its Application

Koichi TANNO; Okihiko ISHIZUKA; Zheng TANG

Ultra-Low Power Two-MOS Virtual-Short Circuit and Its Application

Koichi TANNO, Okihiko ISHIZUKA, Zheng TANG

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In this paper, a virtual-short circuit which consists of only two MOS transistors operated in the weak-inversion region is proposed. It has the advantages of almost zero power consumption, low voltage operation, small chip area, and no needlessness of bias voltages or currents. The second order effects, such as the device mismatch, the Early effect, and the temperature dependency of the circuit are analyzed in detail. Next, current-controlled and voltage-controlled current sources using the proposed virtual-short circuit are presented as applications. The performance of the proposed circuits is estimated using SPICE simulation with MOSIS 1. 2 µm CMOS device parameters. The results are reported on this paper.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.10 pp.2194-2200

Publication Date: 1998/10/25

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Category: Analog Signal Processing

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Koichi TANNO, Okihiko ISHIZUKA, Zheng TANG, "Ultra-Low Power Two-MOS Virtual-Short Circuit and Its Application" in IEICE TRANSACTIONS on Fundamentals, vol. E81-A, no. 10, pp. 2194-2200, October 1998, doi: .
Abstract: In this paper, a virtual-short circuit which consists of only two MOS transistors operated in the weak-inversion region is proposed. It has the advantages of almost zero power consumption, low voltage operation, small chip area, and no needlessness of bias voltages or currents. The second order effects, such as the device mismatch, the Early effect, and the temperature dependency of the circuit are analyzed in detail. Next, current-controlled and voltage-controlled current sources using the proposed virtual-short circuit are presented as applications. The performance of the proposed circuits is estimated using SPICE simulation with MOSIS 1. 2 µm CMOS device parameters. The results are reported on this paper.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e81-a_10_2194/_p

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@ARTICLE{e81-a_10_2194,
author={Koichi TANNO, Okihiko ISHIZUKA, Zheng TANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Ultra-Low Power Two-MOS Virtual-Short Circuit and Its Application},
year={1998},
volume={E81-A},
number={10},
pages={2194-2200},
abstract={In this paper, a virtual-short circuit which consists of only two MOS transistors operated in the weak-inversion region is proposed. It has the advantages of almost zero power consumption, low voltage operation, small chip area, and no needlessness of bias voltages or currents. The second order effects, such as the device mismatch, the Early effect, and the temperature dependency of the circuit are analyzed in detail. Next, current-controlled and voltage-controlled current sources using the proposed virtual-short circuit are presented as applications. The performance of the proposed circuits is estimated using SPICE simulation with MOSIS 1. 2 µm CMOS device parameters. The results are reported on this paper.},
keywords={},
doi={},
ISSN={},
month={October},}

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TY - JOUR
TI - Ultra-Low Power Two-MOS Virtual-Short Circuit and Its Application
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2194
EP - 2200
AU - Koichi TANNO
AU - Okihiko ISHIZUKA
AU - Zheng TANG
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 1998
AB - In this paper, a virtual-short circuit which consists of only two MOS transistors operated in the weak-inversion region is proposed. It has the advantages of almost zero power consumption, low voltage operation, small chip area, and no needlessness of bias voltages or currents. The second order effects, such as the device mismatch, the Early effect, and the temperature dependency of the circuit are analyzed in detail. Next, current-controlled and voltage-controlled current sources using the proposed virtual-short circuit are presented as applications. The performance of the proposed circuits is estimated using SPICE simulation with MOSIS 1. 2 µm CMOS device parameters. The results are reported on this paper.
ER -