Analog Circuit Design Methodology in a Low Power RISC Microprocessor

Koichiro ISHIBASHI; Hisayuki HIGUCHI; Toshinobu SHIMBO; Kunio UCHIYAMA; Kenji SHIOZAWA; Naotaka HASHIMOTO; Shuji IKEDA

Analog Circuit Design Methodology in a Low Power RISC Microprocessor

Koichiro ISHIBASHI, Hisayuki HIGUCHI, Toshinobu SHIMBO, Kunio UCHIYAMA, Kenji SHIOZAWA, Naotaka HASHIMOTO, Shuji IKEDA

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There are various kinds of analog CMOS circuits in microprocessors. IOs, clock distribution circuits including PLL, memories are the main analog circuits. The circuit techniques to achieve low power dissipation combined with high performance in newest prototype chip in the Super H RISC engines are described. A TLB delay can be decreased by using a CAM with a differential amplifier to generate the match signal. The accelerator circuit also helps to speed up the TLB circuit, enabling single-cycle operation. A fabricated 96- mm ² test chip with the super H architecture using 0. 35-µm four metal CMOS technology is capable of 167-MHz operation at 300 Dhrystone MIPS with 2. 0-W power dissipation.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.2 pp.210-217

Publication Date: 1998/02/25

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Type of Manuscript: Special Section INVITED PAPER (Special Section on Analog Circuit Techniques in the Digital-Oriented Era)

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Koichiro ISHIBASHI, Hisayuki HIGUCHI, Toshinobu SHIMBO, Kunio UCHIYAMA, Kenji SHIOZAWA, Naotaka HASHIMOTO, Shuji IKEDA, "Analog Circuit Design Methodology in a Low Power RISC Microprocessor" in IEICE TRANSACTIONS on Fundamentals, vol. E81-A, no. 2, pp. 210-217, February 1998, doi: .
Abstract: There are various kinds of analog CMOS circuits in microprocessors. IOs, clock distribution circuits including PLL, memories are the main analog circuits. The circuit techniques to achieve low power dissipation combined with high performance in newest prototype chip in the Super H RISC engines are described. A TLB delay can be decreased by using a CAM with a differential amplifier to generate the match signal. The accelerator circuit also helps to speed up the TLB circuit, enabling single-cycle operation. A fabricated 96- mm ² test chip with the super H architecture using 0. 35-µm four metal CMOS technology is capable of 167-MHz operation at 300 Dhrystone MIPS with 2. 0-W power dissipation.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e81-a_2_210/_p

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@ARTICLE{e81-a_2_210,
author={Koichiro ISHIBASHI, Hisayuki HIGUCHI, Toshinobu SHIMBO, Kunio UCHIYAMA, Kenji SHIOZAWA, Naotaka HASHIMOTO, Shuji IKEDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Analog Circuit Design Methodology in a Low Power RISC Microprocessor},
year={1998},
volume={E81-A},
number={2},
pages={210-217},
abstract={There are various kinds of analog CMOS circuits in microprocessors. IOs, clock distribution circuits including PLL, memories are the main analog circuits. The circuit techniques to achieve low power dissipation combined with high performance in newest prototype chip in the Super H RISC engines are described. A TLB delay can be decreased by using a CAM with a differential amplifier to generate the match signal. The accelerator circuit also helps to speed up the TLB circuit, enabling single-cycle operation. A fabricated 96- mm ² test chip with the super H architecture using 0. 35-µm four metal CMOS technology is capable of 167-MHz operation at 300 Dhrystone MIPS with 2. 0-W power dissipation.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - Analog Circuit Design Methodology in a Low Power RISC Microprocessor
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 210
EP - 217
AU - Koichiro ISHIBASHI
AU - Hisayuki HIGUCHI
AU - Toshinobu SHIMBO
AU - Kunio UCHIYAMA
AU - Kenji SHIOZAWA
AU - Naotaka HASHIMOTO
AU - Shuji IKEDA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 1998
AB - There are various kinds of analog CMOS circuits in microprocessors. IOs, clock distribution circuits including PLL, memories are the main analog circuits. The circuit techniques to achieve low power dissipation combined with high performance in newest prototype chip in the Super H RISC engines are described. A TLB delay can be decreased by using a CAM with a differential amplifier to generate the match signal. The accelerator circuit also helps to speed up the TLB circuit, enabling single-cycle operation. A fabricated 96- mm ² test chip with the super H architecture using 0. 35-µm four metal CMOS technology is capable of 167-MHz operation at 300 Dhrystone MIPS with 2. 0-W power dissipation.
ER -