Bit and Word-Level Common Subexpression Elimination for the Synthesis of Linear Computations

Akihiro MATSUURA; Akira NAGOYA

Bit and Word-Level Common Subexpression Elimination for the Synthesis of Linear Computations

Akihiro MATSUURA, Akira NAGOYA

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In this paper, we propose a transformation technique for the multiplications of one variable with multiple constants, which are frequently seen in the various applications of signal processing, image processing, and so forth. The method is based on the exploration of common subexpressions among constants and reduces the number of shifts, additions, and subtractions to implement linear computations with hardware. Our method searches for regularity among elements of a linear transform using matrix decomposition and generates a reduced data-flow graph which preserves the full regularity. We show experimental results obtained using Discrete Cosine Transform (DCT) and Fast Fourier Transform (FFT) and illustrate the effectiveness of the method.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.3 pp.455-461

Publication Date: 1998/03/25

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Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 10th Karuizawa Workshop on Circuits and Systems)

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Akihiro MATSUURA, Akira NAGOYA, "Bit and Word-Level Common Subexpression Elimination for the Synthesis of Linear Computations" in IEICE TRANSACTIONS on Fundamentals, vol. E81-A, no. 3, pp. 455-461, March 1998, doi: .
Abstract: In this paper, we propose a transformation technique for the multiplications of one variable with multiple constants, which are frequently seen in the various applications of signal processing, image processing, and so forth. The method is based on the exploration of common subexpressions among constants and reduces the number of shifts, additions, and subtractions to implement linear computations with hardware. Our method searches for regularity among elements of a linear transform using matrix decomposition and generates a reduced data-flow graph which preserves the full regularity. We show experimental results obtained using Discrete Cosine Transform (DCT) and Fast Fourier Transform (FFT) and illustrate the effectiveness of the method.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e81-a_3_455/_p

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@ARTICLE{e81-a_3_455,
author={Akihiro MATSUURA, Akira NAGOYA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Bit and Word-Level Common Subexpression Elimination for the Synthesis of Linear Computations},
year={1998},
volume={E81-A},
number={3},
pages={455-461},
abstract={In this paper, we propose a transformation technique for the multiplications of one variable with multiple constants, which are frequently seen in the various applications of signal processing, image processing, and so forth. The method is based on the exploration of common subexpressions among constants and reduces the number of shifts, additions, and subtractions to implement linear computations with hardware. Our method searches for regularity among elements of a linear transform using matrix decomposition and generates a reduced data-flow graph which preserves the full regularity. We show experimental results obtained using Discrete Cosine Transform (DCT) and Fast Fourier Transform (FFT) and illustrate the effectiveness of the method.},
keywords={},
doi={},
ISSN={},
month={March},}

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TY - JOUR
TI - Bit and Word-Level Common Subexpression Elimination for the Synthesis of Linear Computations
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 455
EP - 461
AU - Akihiro MATSUURA
AU - Akira NAGOYA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 1998
AB - In this paper, we propose a transformation technique for the multiplications of one variable with multiple constants, which are frequently seen in the various applications of signal processing, image processing, and so forth. The method is based on the exploration of common subexpressions among constants and reduces the number of shifts, additions, and subtractions to implement linear computations with hardware. Our method searches for regularity among elements of a linear transform using matrix decomposition and generates a reduced data-flow graph which preserves the full regularity. We show experimental results obtained using Discrete Cosine Transform (DCT) and Fast Fourier Transform (FFT) and illustrate the effectiveness of the method.
ER -