Complete Diagnosis Patterns for Wiring Interconnects

Sungju PARK; Gueesang LEE

Complete Diagnosis Patterns for Wiring Interconnects

Sungju PARK, Gueesang LEE

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It is important to test the various kinds of interconnect faults between chips on a card/module. When boundary scan design techniques are adopted, the chip to chip interconnection test generation and application of test patterns is greatly simplified. Various test generation algorithms have been developed for interconnect faults. A new interconnect test generation algorithm is introduced. It reduces the number of test patterns by half over present techniques. It also guarantees the complete diagnosis of multiple interconnect faults.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.4 pp.672-676

Publication Date: 1998/04/25

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Category: VLSI Design Technology and CAD

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Sungju PARK, Gueesang LEE, "Complete Diagnosis Patterns for Wiring Interconnects" in IEICE TRANSACTIONS on Fundamentals, vol. E81-A, no. 4, pp. 672-676, April 1998, doi: .
Abstract: It is important to test the various kinds of interconnect faults between chips on a card/module. When boundary scan design techniques are adopted, the chip to chip interconnection test generation and application of test patterns is greatly simplified. Various test generation algorithms have been developed for interconnect faults. A new interconnect test generation algorithm is introduced. It reduces the number of test patterns by half over present techniques. It also guarantees the complete diagnosis of multiple interconnect faults.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e81-a_4_672/_p

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@ARTICLE{e81-a_4_672,
author={Sungju PARK, Gueesang LEE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Complete Diagnosis Patterns for Wiring Interconnects},
year={1998},
volume={E81-A},
number={4},
pages={672-676},
abstract={It is important to test the various kinds of interconnect faults between chips on a card/module. When boundary scan design techniques are adopted, the chip to chip interconnection test generation and application of test patterns is greatly simplified. Various test generation algorithms have been developed for interconnect faults. A new interconnect test generation algorithm is introduced. It reduces the number of test patterns by half over present techniques. It also guarantees the complete diagnosis of multiple interconnect faults.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - Complete Diagnosis Patterns for Wiring Interconnects
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 672
EP - 676
AU - Sungju PARK
AU - Gueesang LEE
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 1998
AB - It is important to test the various kinds of interconnect faults between chips on a card/module. When boundary scan design techniques are adopted, the chip to chip interconnection test generation and application of test patterns is greatly simplified. Various test generation algorithms have been developed for interconnect faults. A new interconnect test generation algorithm is introduced. It reduces the number of test patterns by half over present techniques. It also guarantees the complete diagnosis of multiple interconnect faults.
ER -