Multi-cycle Test looks promising a way to reduce the test application time of POST (Power-on Self-Test) for achieving a targeted high fault coverage specified by ISO26262 for testing automotive devices. In this paper, we first analyze the mechanism of Stuck-at Fault Detection Degradation problem in multi-cycle test. Based on the result of our analysis we propose a novel solution named FF-Control Point Insertion technique (FF-CPI) to achieve the reduction of scan-in patterns by multi-cycle test. The FF-CPI technique modifies the captured values of scan Flip-Flops (FFs) during capture operation by directly reversing the value of partial FFs or loading random vectors. The FF-CPI technique enhances the number of detectable stuck-at faults under the capture patterns. The experimental results of ISCAS89 and ITC99 benchmarks validated the effectiveness of FF-CPI technique in scan-in pattern reduction for POST.

Embedded software developers assume the behavior of the environment when specifications are not available. However, developers may assume the behavior incorrectly, which may result in critical faults in the system. Therefore, it is important to detect the faults caused by incorrect assumptions. In this letter, we propose a log-based testing approach to detect the faults. First, we create a UML behavioral model to represent the assumed behavior of the environment, which is then transformed into a state model. Next, we extract the actual behavior of the environment from a log, which is then incorporated in the state model, resulting in a state model that represents both assumed and actual behaviors. Existing testing techniques based on the state model can be used to generate test cases from our state model to detect faults.

Since the sensor nodes are subject to faults due to the highly-constrained resources and hostile deployment environments, fault management in wireless sensor networks (WSNs) is essential to guarantee the proper operation of networks, especially routing. In contrast to existing fault management methods which mainly aim to be tolerant to faults without considering the fault type, we propose a novel efficient fault-aware routing method where faults are classified and dealt with accordingly. More specifically, we first identify each fault and then try to set up the new routing path according to the fault type. Our proposed method can be easily integrated with any kind of existing routing method. We show that our proposed method outperforms AODV, REAR, and GPSR, which are the representative works of single-path routing, multipath routing and location based routing, in terms of energy efficiency and data delivery ratio.

Timing fault detection techniques address the problems caused by increased variations on a chip, especially with dynamic voltage and frequency scaling (DVFS). The Razor flip-flop (FF) is a timing fault detection technique that employs double sampling by the main and shadow FFs. In order for the Razor FF to correctly detect a timing fault, not the main FF but the shadow FF must sample the correct value. The application of Razor FFs to static logic relaxes the timing constraints; however, the naive application of Razor FFs to dynamic precharged logic such as SRAM read circuits is not effective. This is because the SRAM precharge cannot start before the shadow FF samples the value; otherwise, the transition of the bitline of the SRAM stops and the value sampled by the shadow FF will be incorrect. Therefore, the detect period cannot overlap the precharge period. This paper proposes a novel application of Razor FFs to SRAM read circuits. Our proposal employs a conditional precharge according to the value of a bitline sampled by the main FF. This enables the detect period to overlap the precharge period, thereby relaxing the timing constraints. The additional circuit required by this method is simple and only needed around the sense amplifier, and there is no need for a clock delayed from the system clock. Consequently, the area overhead of the proposed circuit is negligible. This paper presents SPICE simulations of the proposed circuit. Our proposal reduces the minimum cycle time by 51.5% at a supply voltage of 1.1 V and the minimum voltage by 31.8% at cycle time of 412.5 ps.

This paper presents a new strategy to detect and diagnose fault of a manipulator based on the expression with a Probabilistic Production Rule (PPR). Production Rule (PR) is widely used in the field of computer science as a tool of formal verification. In this work, first of all, PR is used to represent the mapping between highly quantized input and output signals of the dynamical system. By using PR expression, the fault detection and diagnosis algorithm can be implemented with less computational effort. In addition, we introduce a new system description with Probabilistic PR (PPR) wherein the occurrence probability of PRs is assigned to them to improve the robustness with small computational burden. The probability is derived from the statistic characteristics of the observed input and output signals. Then, the fault detection and diagnosis algorithm is developed based on calculating the log-likelihood of the measured data for the designed PPR. Finally, some experiments on a controlled manipulator are demonstrated to confirm the usefulness of the proposed method.

This paper presents a new bearing fault detection algorithm based on analyzing singular points of vibration signals using the Haar wavelet. The proposed Haar Fault Detection (HFD) algorithm is compared with a previously-developed algorithm associated with the Morlet wavelet. We also substitute the Haar wavelet with Daubechies wavelets with larger compact supports and evaluate the results. Simulations carried on real data demonstrate that the HFD algorithm achieves a comparable accuracy while having a lower computational cost. This makes the HFD algorithm an appropriate candidate for fast processing of bearing faults.

Comparison of intelligent and random testing in data inputting is still under discussion. Little is also known about testing for the whole software and empirical testing methodology when random testing used. This study research not only for data inputting testing, but also operation of software (called transitions) in order to test the whole GUI software by intelligent and random testing. Methodology of this study is that we attempt to research efficiency of random and intelligent testing by Chinese postman problem. In general, random testing is considered straightforward but not efficient. Chinese postman problem testing is complicated but efficient. The comparison between random and intelligent testing would give further recommendation for software testing methodology.

Coefficient-based test (CBT) is introduced for detecting parametric faults in analog circuits. The method uses pseudo Monte-Carlo simulation and system identification tools to determine whether a given circuit under test (CUT) is faulty.

The network duplicating can achieve significant improvements of the Local Area Network (LAN)'s performance, availability, and security. For LAN duplicating, a Dual-Path Ethernet Module (DPEM) is developed. Since a DPEM is simply located at the front end of any network device as a transparent add-on type independent hardware machine, it does not require sophisticated server reconfiguration. We examine the desirable properties and the characteristics on the Dual-LAN structure. Our evaluation results show that the developed scheme is more efficient than the conventional Single-LAN structures in various aspects.

The programming circuit of SRAM-based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We first derive test procedures for the shift registers, which can be done by using only the faculties of the programming circuit, without using additional hardware. Next, we show the validness of the test procedures. Finally, we show an application of the test procedures to test Xilinx XC4025.

This paper treats a fault detection/location of multi-processor systems, and we present a checking scheme based on Modified Processor-Data (MPD) graph with considering an error generation/propagation model for Algorithm-Based Fault Tolerant (ABFT) systems. The error propagation model considered here allows a computation result with multiple (more than one) erroneous inputs to be either erroneous or error-free. Also a basic algorithm for constructing checks for single-fault locatable/two-fault detectable ABFT systems based on the checking scheme is described with design examples.

It is important to test the various kinds of interconnect faults between chips on a card/module. When boundary scan design techniques are adopted, the chip to chip interconnection test generation and application of test patterns is greatly simplified. Various test generation algorithms have been developed for interconnect faults. A new interconnect test generation algorithm is introduced. It reduces the number of test patterns by half over present techniques. It also guarantees the complete diagnosis of multiple interconnect faults.

This paper discribes the ISDN PROtocol Testing system (I-PROT). The system consists of translation & distribution function block, layer-2 fault surveillance function block, layer-3 fault surveillance function block, cause detection function block, and HMI. The system receives data from protocol monitors and detects the error recovery sequences, (we call "quasi-normal sequences"), as well as the sequences that do not follow the protocol specifications, (we call "abnormal sequences"). In the layer-3 fault surveillance function block, we use the protocol specification database whose records are converted from the state transition rules and added the judgment which classify the rules into the "normal" and "quasi-normal." We also show the classification method which is applicable to all connection-oriented protocol specifications. In the layer-2 fault surveillance function block, we explain the another easy detecting method. In the cause function block, we describe the partial pattern matching method to relate the protocol fault to the real cause of the fault. We built the prototype of the I-PROT and examine the turn around time (TAT) performance. As a result of the examination, we find the TAT of the I-PROT is directly proportional to the number of the frames analyzed by the system, and the system can reduce the load of the conventional manual analysis by the maintenance personnel.

Synthesis tools are now extensively used in the VLSI circuit design process. They allow a much higher design productivity, but the designer often does not directly control the circuit structure. Thus, when circuits are dedicated to dependable applications, designers have difficulties in implementing manually the devices needed to obtain fault detection or tolerance capabilities. The ASYL-SdF System has been developed over the last few years in order to avoid this break in the design flow, and to facilitate the designer's work when dependability is targeted. This paper gives an overview of the resulting tool, its synthesis flow for fault detection and fault tolerance in Finite State Machines, its limitations and the current developments. Actual circuit implementation results are given in terms of area overheads, expected reliability and experimental fault detection coverage.

This paper describes a new method for the concurrent detection of faults in instruction level parallel (ILP) processors. This method uses the No OPeration (NOP) instruction slots that under branches, resource conflicts and some kind of data dependencies fill some of the pipelines (stages) in an ILP processor. NOPs are replaced by the copy of an effective instruction running in another pipeline. This allows the checking of the pipelines running the original instruction and its copy (ies), by the comparison of the outputs of their stages during the execution of the replicated instruction. We show some figures obtained for the application of this method to a two-pipeline superscalar processor.

Advances in semiconductor technology have made it possible to develop an experimental 1000 MIPS superscalar RISC processor. The high performance of this processor was obtained using architectural concepts such as multiple CPU configuration, superscalar microarchitecture, and high-speed device technology. This paper focuses on the novel features of this RISC processor, its device technology, architectural characteristics and one technology that has been devised to make its integer CPU cores fault-tolerant.