8-mW, 1-V, 100-MSample/s, 6-bit A/D Converter Using a Latched Comparator Operating in the Triode Region

Jun TERADA; Yasuyuki MATSUYA; Fumiharu MORISAWA; Yuichi KADO

8-mW, 1-V, 100-MSample/s, 6-bit A/D Converter Using a Latched Comparator Operating in the Triode Region

Jun TERADA, Yasuyuki MATSUYA, Fumiharu MORISAWA, Yuichi KADO

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A very low-power, high-speed flash A/D converter front-end composed of a new latched comparator was developed. We established a butterfly sorting technique to guarantee the monotonicity of the converter. The 6-bit A/D front-end achieves a speed of 100 Msps and dynamic range of 33 dB with power consumption of only 7 mW at the supply voltage of 1 V, and the butterfly sorter guarantees 6-bit monotonicity with an extra power consumption of 1 mW.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.2 pp.313-317

Publication Date: 2003/02/01

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Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)

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Jun TERADA, Yasuyuki MATSUYA, Fumiharu MORISAWA, Yuichi KADO, "8-mW, 1-V, 100-MSample/s, 6-bit A/D Converter Using a Latched Comparator Operating in the Triode Region" in IEICE TRANSACTIONS on Fundamentals, vol. E86-A, no. 2, pp. 313-317, February 2003, doi: .
Abstract: A very low-power, high-speed flash A/D converter front-end composed of a new latched comparator was developed. We established a butterfly sorting technique to guarantee the monotonicity of the converter. The 6-bit A/D front-end achieves a speed of 100 Msps and dynamic range of 33 dB with power consumption of only 7 mW at the supply voltage of 1 V, and the butterfly sorter guarantees 6-bit monotonicity with an extra power consumption of 1 mW.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e86-a_2_313/_p

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@ARTICLE{e86-a_2_313,
author={Jun TERADA, Yasuyuki MATSUYA, Fumiharu MORISAWA, Yuichi KADO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={8-mW, 1-V, 100-MSample/s, 6-bit A/D Converter Using a Latched Comparator Operating in the Triode Region},
year={2003},
volume={E86-A},
number={2},
pages={313-317},
abstract={A very low-power, high-speed flash A/D converter front-end composed of a new latched comparator was developed. We established a butterfly sorting technique to guarantee the monotonicity of the converter. The 6-bit A/D front-end achieves a speed of 100 Msps and dynamic range of 33 dB with power consumption of only 7 mW at the supply voltage of 1 V, and the butterfly sorter guarantees 6-bit monotonicity with an extra power consumption of 1 mW.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - 8-mW, 1-V, 100-MSample/s, 6-bit A/D Converter Using a Latched Comparator Operating in the Triode Region
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 313
EP - 317
AU - Jun TERADA
AU - Yasuyuki MATSUYA
AU - Fumiharu MORISAWA
AU - Yuichi KADO
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2003
AB - A very low-power, high-speed flash A/D converter front-end composed of a new latched comparator was developed. We established a butterfly sorting technique to guarantee the monotonicity of the converter. The 6-bit A/D front-end achieves a speed of 100 Msps and dynamic range of 33 dB with power consumption of only 7 mW at the supply voltage of 1 V, and the butterfly sorter guarantees 6-bit monotonicity with an extra power consumption of 1 mW.
ER -