An analytical method to make a trade off between tuning range and differential non-linearity (DNL) for a digitally controlled oscillator (DCO) is proposed. To verify the approach, a 12 bit DCO is designed, implemented in 0.18 µm CMOS technology, and tested. The measured DNL was -0.41 Least Significant Bit (LSB) without degrading other parameters which is the best so far among the reported DCOs.

Yubazaki et al. have proposed "single input rule modules connected type fuzzy reasoning method" (SIRMs method, for short) whose final output is obtained by summarizing the product of the importance degrees and the inference results from single input fuzzy rule module. Another type of single input type fuzzy reasoning method proposed by Hayashi et al. (we call it "Single Input Connected fuzzy reasoning method" (SIC method, for short) in this paper) uses rule modules to each input item as well as SIRMs method. We expect that inference results of SIRMs method and SIC method have monotonicity if the antecedent parts and consequent parts of fuzzy rules in SIRMs rule modules have monotonicity. However, this paper points out that even if fuzzy rules in SIRMs rule modules have monotonicity, the inference results do not necessarily have monotonicity. Moreover, it clarifies the conditions for the monotonicity of inference results by SIRMs method and SIC method.

The knowledge of a good enclosure of the range of a function over small interval regions allows us to avoid convergence of optimization algorithms to a non-global point(s). We used interval slopes f[X,x] to check for monotonicity and integrated their derivative forms g[X,x], x X by quadratic and Newton methods to obtain narrow enclosures. In order to include boundary points in the search for the optimum point(s), we expanded the initial box by a small width on each dimension. These procedures resulted in an improvement in the algorithm proposed by Hansen.

A very low-power, high-speed flash A/D converter front-end composed of a new latched comparator was developed. We established a butterfly sorting technique to guarantee the monotonicity of the converter. The 6-bit A/D front-end achieves a speed of 100 Msps and dynamic range of 33 dB with power consumption of only 7 mW at the supply voltage of 1 V, and the butterfly sorter guarantees 6-bit monotonicity with an extra power consumption of 1 mW.

In this paper, we focus on regularity and set-valued functions. Regularity was first introduced by S. C. Kleene in the propositional operations of his ternary logic. Then, M. Mukaidono investigated some properties of ternary functions, which can be represented by regular operations. He called such ternary functions "regular ternary logic functions". Regular ternary logic functions are useful for representing and analyzing ambiguities such as transient states or initial states in binary logic circuits that Boolean functions cannot cope with. Furthermore, they are also applied to studies of fail-safe systems for binary logic circuits. In this paper, we will discuss an extension of regular ternary logic functions into r-valued set-valued functions, which are defined as mappings on a set of nonempty subsets of the r-valued set {0, 1, . . . , r-1}. First, the paper will show a method by which operations on the r-valued set {0, 1, . . . , r-1} can be expanded into operations on the set of nonempty subsets of {0, 1, . . . , r-1}. These operations will be called regular since this method is identical with the way that Kleene expanded operations of binary logic into his ternary logic. Finally, explicit expressions of set-valued functions monotonic in subset will be presented.

This paper presents some fundamental properties of multiple-valued logic functions monotonic in a partial-ordering relation which is introduced in the set of truth values and does not necessarily have the greatest or least element. Two kinds of necessary and sufficient conditions for monotonic p-valued functions are given with the proofs. Their logic formulas using unary operators defined in the partial-ordering relation and a simplification method for those logic formulas are also given. These results include as their special cases our former results for p-valued functions monotonic in the ambiguity relation which is a partial-ordering relation with the greatest element.

This paper presents a new piecewise-linear dc model of the MOSFET. The proposed model is derived for long channel MOSFETs from the Shichman-Hodges equations, with emphasis on the accurate modeling of the major electrical characteristics, and is extended for short channel MOSFETs. The performance of the model is evaluated by comparing current-voltage characteristics and voltage transfer characteristics with those of the SPICE level-l and Sakurai models. The experimental results, using three or fewer piecewise-linear region boundaries on the axes of VGS, VGD and VSB, demonstrate that the proposed model provides enough accuracy for practical use with digital circuits.

The paper considers multiple-valued logic systems having the property that the ambiguity of the system increases as the ambiguity of each component increases. The partial-ordering relation with respect to ambiguity with the greatest element 1/2 and minimal elements 0, 1 or simply the ambiguity relation is introduced in the set of truth values V {0, 1/ (p1), , 1/2, , (p2) / (p1), 1}. A-monotonic p-valued logic functions are defined as p-valued logic functions monotonic with respect to the ambiguity relation. A necessary and sufficient condition for A-monotonic p-valued logic functions is presented along with the proofs, and their logic formulae using unary operators defined in the ambiguity relation are given. Some discussions on the extension of theories to other partial-ordering relations are also given.