Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence

Kenichi OKADA; Hidetoshi ONODERA

Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence

Kenichi OKADA, Hidetoshi ONODERA

Full Text Views

0

Share
Cite this

Summary :

The main purpose of our method is to obtain realistic worst-case delay in statistical timing analyses. This paper proposes a method of statistical delay calculation based on measured intra-chip and inter-chip variabilities. We present a modeling and extracting method of transistor characteristics for the intra-chip variability and the inter-chip variability. In the modeling of the intra-chip variability, it is important to consider a gate-size dependence by which the amount of intra-chip variation is affected. This effect is not captured in a statistical delay analysis reported so far. Our method proposes a method for modeling of the device variability and statistical delay calculation with consideration of the size dependence, and uses a response surface method (RSM) to calculate a delay variation with low processing cost. We evaluate the accuracy of our method, and we show some experimental results the variation of a circuit delay characterized by the measured variances of transistor currents.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.4 pp.746-751

Publication Date: 2003/04/01

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)

Category

Cite this

Copy

Kenichi OKADA, Hidetoshi ONODERA, "Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence" in IEICE TRANSACTIONS on Fundamentals, vol. E86-A, no. 4, pp. 746-751, April 2003, doi: .
Abstract: The main purpose of our method is to obtain realistic worst-case delay in statistical timing analyses. This paper proposes a method of statistical delay calculation based on measured intra-chip and inter-chip variabilities. We present a modeling and extracting method of transistor characteristics for the intra-chip variability and the inter-chip variability. In the modeling of the intra-chip variability, it is important to consider a gate-size dependence by which the amount of intra-chip variation is affected. This effect is not captured in a statistical delay analysis reported so far. Our method proposes a method for modeling of the device variability and statistical delay calculation with consideration of the size dependence, and uses a response surface method (RSM) to calculate a delay variation with low processing cost. We evaluate the accuracy of our method, and we show some experimental results the variation of a circuit delay characterized by the measured variances of transistor currents.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e86-a_4_746/_p

Copy

@ARTICLE{e86-a_4_746,
author={Kenichi OKADA, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence},
year={2003},
volume={E86-A},
number={4},
pages={746-751},
abstract={The main purpose of our method is to obtain realistic worst-case delay in statistical timing analyses. This paper proposes a method of statistical delay calculation based on measured intra-chip and inter-chip variabilities. We present a modeling and extracting method of transistor characteristics for the intra-chip variability and the inter-chip variability. In the modeling of the intra-chip variability, it is important to consider a gate-size dependence by which the amount of intra-chip variation is affected. This effect is not captured in a statistical delay analysis reported so far. Our method proposes a method for modeling of the device variability and statistical delay calculation with consideration of the size dependence, and uses a response surface method (RSM) to calculate a delay variation with low processing cost. We evaluate the accuracy of our method, and we show some experimental results the variation of a circuit delay characterized by the measured variances of transistor currents.},
keywords={},
doi={},
ISSN={},
month={April},}

Copy

TY - JOUR
TI - Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 746
EP - 751
AU - Kenichi OKADA
AU - Hidetoshi ONODERA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2003
AB - The main purpose of our method is to obtain realistic worst-case delay in statistical timing analyses. This paper proposes a method of statistical delay calculation based on measured intra-chip and inter-chip variabilities. We present a modeling and extracting method of transistor characteristics for the intra-chip variability and the inter-chip variability. In the modeling of the intra-chip variability, it is important to consider a gate-size dependence by which the amount of intra-chip variation is affected. This effect is not captured in a statistical delay analysis reported so far. Our method proposes a method for modeling of the device variability and statistical delay calculation with consideration of the size dependence, and uses a response surface method (RSM) to calculate a delay variation with low processing cost. We evaluate the accuracy of our method, and we show some experimental results the variation of a circuit delay characterized by the measured variances of transistor currents.
ER -