In a previous study about a combinatorial optimization problem solver using neural networks, since the Hopfield method, convergence to the optimum solution sooner and with more certainty is regarded as important. Namely, only static states are considered as the information. However, from a biological point of view, dynamical systems have attracted attention recently. Therefore, we propose a "dynamical" combinatorial optimization problem solver using hysteresis neural networks. In this paper, the proposed system is evaluated by the N-Queen problem.

The main purpose of our method is to obtain realistic worst-case delay in statistical timing analyses. This paper proposes a method of statistical delay calculation based on measured intra-chip and inter-chip variabilities. We present a modeling and extracting method of transistor characteristics for the intra-chip variability and the inter-chip variability. In the modeling of the intra-chip variability, it is important to consider a gate-size dependence by which the amount of intra-chip variation is affected. This effect is not captured in a statistical delay analysis reported so far. Our method proposes a method for modeling of the device variability and statistical delay calculation with consideration of the size dependence, and uses a response surface method (RSM) to calculate a delay variation with low processing cost. We evaluate the accuracy of our method, and we show some experimental results the variation of a circuit delay characterized by the measured variances of transistor currents.

This paper proposes a low power consumption Analog Matched Filter (AMF) that utilizes capacitor multiply-and-accumulate operations. A high-speed, high-precision Analog-to-Digital (A/D) converter is unnecessary because the proposed circuit directly samples received analog signals. A code-shifting MF structure is used to prevent errors from accumulating. A 15-tap AMF circuit was fabricated using 0.35 µm CMOS technology. Power consumption for the 128-tap circuit is estimated to be 22.3 mW at 25 MHz and 3.3 V, and the area is estimated to be 0.33 mm². The proposed circuit will thus be a useful LSI for mobile terminals.

A linear voltage-to-current convertor without current mirror circuit is proposed for low distortion applications employing short channel MOSFET's. Twin current sources and current sinks pair of MOSFET's having the same drain-source voltage are employed for a substitute of the current mirror circuits, in order to eliminate the channel length modulation factor of the short channel MOSFET's. HSPICE simulation is shown in order to evaluate the proposed circuits. As an application, a low distortion OTA is realized by employing the proposed linear voltage-to-current convertor with short channel MOSFET's.

In this paper, we propose a function that provides scalability of image quality on the basis of regions of interest for JPEG2000 coding. Functions of this type are useful in the progressive transmission of images, where the aim is to more quickly decode regions of interest than backgrounds. The conventional methods of progressive transmission have mainly been based on SNR scalability or on resolution scalability. With these conventional functions, it is impossible to achieve region-based scalability in the progressive transmission of images. The proposed methods use the ROI and SNR layer structures of JPEG2000, so the methods are suitable for the region-progressive transmission of JPEG2000 images.

A method of error concealment for JPEG2000 images is proposed in this paper. The proposed method uses the layer structure that is a feature of the JPEG2000. The most significant layer is hidden in the lowest layer of the JPEG2000 bit stream, and this embedded layer is used for error concealment. The most significant layer is duplicated because JPEG2000 uses bit-plane coding. In this coding, when the upper layers are affected by errors, the coefficients of the lower layers become meaningless. A bit stream encoded using the proposed method has the same data structure as a standard JPEG2000. Therefore, it can be decoded by a standard decoder. Our simulation results demonstrated the effectiveness of the proposed method.

Several lifting implementation techniques for invertible deniterlacing are proposed in this paper. Firstly, the invertible deinterlacing is reviewed, and an efficient implementation is presented. Next, two deinterlacer-embedded lifting architectures of discrete wavelet transforms (DWT) is proposed. Performances are compared among several architectures of deinterlacing with DWT. The performance evaluation includes dual-multiplier and single-multiplier architectures. The number of equivalent gates shows that the deinterlacing-embedded architectures require less resources than the separate implementaion. Our experimental evaluation of the dual-multiplier architecture results in 0.8% increase in the gate count, whereas the separate implementation of deinterlacing and DWT requires 6.1% increase from the normal DWT architecture. For the proposed single-multiplier architecture, the gate count is shown to result in 4.5% increase, while the separate counterpart yields 10.7% increase.

This paper describes the effects of system LSI design with C language-based behavioral synthesis following several trials of design period reduction and quality improvement for a variety of circuit types. The results of these trials are analyzed from the viewpoints of description productivity, verification productivity, reusability and design flexibility as well as hardware and software co-verification. First the C-based design flow proposed by the authors is described, and the design productivity and verification productivity under this design flow is compared to RTL design. The reusability of the behavioral IP core and its efficiency with HW/SW co-verification are also shown using design examples. Next, using the example of an MPEG-4 video decoder design, a typical design process in a C-based design is shown with considerations regarding verification efficiency, reusability of the IP core and HW/SW co-verification. Finally, the authors' perspectives regarding future directions of system LSI design are discussed.

In this paper, we propose an instruction encoding scheme to reduce power consumption of instruction ROMs. The power consumption of the instruction ROM strongly depends on the switching activity of bit-lines due to their large load capacitance. In our approach, the binary-patterns to be assigned as op-codes are determined based on the frequency of instructions in order to reduce the number of bit-line dis-charging. Simulation results show that our approach can reduce 40% of bit-line switchings from a conventional organization.

The present paper addresses the design of manufacturing systems. A resource planning and task allocation problem is proposed, and a multi-agent system for this problem is discussed. In the multi-agent system, an agent exists for each resource and for each operation. The proposed multi-agent system improves the quality of resulting plans by the learning of these agents.

In recent years, information devices with network communication ability have become very popular, and many people actually own such kind of devices. Those information devices, however, do not share users' data in spite of their communication ability. This paper proposes "OCEAN: Object Communication Environment for Arbitrary Network" architecture, which provides liaison of objects stored in each device according to their profiles and situations. It eliminates redundant user operation on information devices, and enables novel communication scheme among users by sharing common objects in those devices. Furthermore, it maximizes the effective use of each device's limitation according to each environment. Finally, in this paper, we discuss our prototype of OCEAN.

The 2-vertex-connectivity augmentation problem for specified vertices (2VCA-SV) is defined as follows: Given an undirected graph G=(V,E), a subgraph G₀=(V,E') of G, a specified set of vertices S V and a weight function w:E R^+ (nonnegative real numbers), find a set E" E-E' with the minimum total weight, such that G₀+E"=(V,E' E") has at least two internally disjoint paths between any pair of vertices in S. In this paper, we propose an O(|V||E|+ |V|² log |V|) time algorithm 2-ABIS, whose performance ratio is 2 (3, respectively), for 2VCA-SV if G₀ has a connected component containing S (otherwise).

A "based" plane triangulation is a plane triangulation with one designated edge on the outer face. In this paper we give a simple algorithm to generate all biconnected based plane triangulations with at most n vertices and with maximum degree at most D. The algorithm uses O(n) space and generates such triangulations in O(1) time per triangulation without duplications. The algorithm does not output entire triangulation but the difference from the previous triangulation. By modifying the algorithm we can generate all biconnected based plane triangulations with exactly n vertices and maximum degree at most D in O(1) time per triangulation, and all biconnected (non-based) plane triangulations with exactly n vertices and maximum degree at most D in O(n³) time per triangulation without duplications.

The label placement problem is one of the most important problems in geographic information systems, cartography, graph drawing and graphical interface design. In this paper, we consider the problem of labeling points and curves in maps drawn from digital data. In digital maps, a curve is represented as a set of points and consists of many small segments. The label for each curve must be placed alongside the corresponding curve. We define a continuous labeling space for points and curves, and present an algorithm using this space for positioning labels. Computational results for subway and JR train maps in Tokyo are presented.

A formula-based approach for extracting the inductance of on-chip VLSI interconnections is presented. All of the formulae have been previously proposed and are well-known, but the degrees of accuracy they provide in this context have not previously been examined. The accuracy of the equations for a 0.1 µm technology node is evaluated through comparison of their results with those of 3-D field solvers. Comprehensive evaluation has proven that the maximum relative error of self- and mutual inductances as calculated by the formulae are less than 5% for parallel wires and less than 13% for angled wires, when wire width is limited to no more than 10 times the minimum. When applied to a realistic example with 43 wire segments, a program using the formula-based approach extracts values more than 60 times faster than a 3-D field solver.

We propose a new algorithm for blind source separation (BSS), in which frequency-domain independent component analysis (FDICA) and time-domain ICA (TDICA) are combined to achieve a superior source-separation performance under reverberant conditions. Generally speaking, conventional TDICA fails to separate source signals under heavily reverberant conditions because of the low convergence in the iterative learning of the inverse of the mixing system. On the other hand, the separation performance of conventional FDICA also degrades significantly because the independence assumption of narrow-band signals collapses when the number of subbands increases. In the proposed method, the separated signals of FDICA are regarded as the input signals for TDICA, and we can remove the residual crosstalk components of FDICA by using TDICA. The experimental results obtained under the reverberant condition reveal that the separation performance of the proposed method is superior to those of TDICA- and FDICA-based BSS methods.

This paper presents the design considerations for a digital dental X-ray system with a commercial CCD sensor. Especially the system should be able to work with several X-ray machines even with them for the classical film. The hardware-software co-design methodology is employed to optimize the system. The full digital implementation is assumed for the reliability of the system. The considered functions cover the pre-processing such as the exposure detection, clamping and the dark level correction and the post-processing such as gray level compensation. It is analyzed with some other constraints in order to make the final partition. The entire system based on the partition will be described.

This paper presents an observer design methodology for a special class of MIMO nonlinear systems. First, we characterize the class of MIMO nonlinear systems that consists of the linear observable part and the nonlinear part with a block triangular structure. Also, the similarity transformation that plays an important role in proving the convergence of the proposed observer is generalized to MIMO systems. Since the gain of the proposed observer minimizes a nonlinear part of the system to suppress for the stability of the error dynamics, it improves the transient performance of the high gain observer. Moreover, by using the generalized similarity transformation, it is shown that under some observability and boundedness conditions, the proposed observer guarantees the global exponential convergence to zero of the estimation error. Finally, the simulation results for induction motor are included to illustrate the validity of our design scheme.

The paper is concerned with an identification-based predistortion scheme for compensating nonlinearity of high power amplifiers (HPA). The identification algorithms for the Wiener-Hammerstein nonlinear model are developed in the frequency domain. By approximately modeling the nonlinear distortion part in HPA by polynomial or spline functions, and introducing linear distortion parts in the input and output of the nonlinear element, the iterative identification schemes are proposed to estimate all the uncertain parameters and to construct an inverse system for the predistortion.

Effects of high-frequency cyclic input and noise on interspike intervals in the coupled Bonhoeffer-van der Pol (BVP) model are studied with computer simulation. When two BVP elements are weakly coupled and cyclic input or noise is added to the first element, the interspike intervals of the second element decrease non-monotonically as the amplitude of the input increases. Further, complicated bifurcations in the interspike intervals are caused by cyclic input in the coupled BVP model in the oscillating state. Effects of the coupling on small rotations due to noise and the interruption of oscillations due to cyclic input, which occur when the equilibrium point is close to the critical point, are also studied. The non-monotonic changes and bifurcations in the interspike intervals are attributed to the phase locking of the coupled elements.

In this study, wave propagation phenomena of phase differences observed in van der Pol oscillators coupled by inductors as a ladder are investigated. The phenomena are called "phase waves. " We classify the observed phenomena and analyze the difference in detail. We observe that the behavior of the phase waves generated by giving a phase difference of positive value is different from the behavior of those generated by giving a phase difference of negative value. We can also observe the generation of two pairs of phase waves. We clarify the mechanisms of these complicated phenomena. Finally, for the case of nine oscillators, we carry out both computer calculations and circuit experiments. Circuit experimental results agree well with computer calculated results qualitatively.

The Quasi-Delay-Insensitive (QDI) model assumes that all the forks are isochronic. The isochronic-fork assumption requires uniform wire delays and uniform switching thresholds of the gates associated with the forking branches. This paper presents a method for determining such forks that do not have to satisfy the isochronic fork requirements, and presents experimental results that show many isochronic forks assumed for existing QDI circuits do not actually have to be "isochronic" or can be even ignored.

A heterogeneous parallel computing environment consisting of different types of workstations and communication links plays an important role in parallel computing. In many applications on the system, collective communication operations are commonly used as communication primitives. Thus, design of the efficient collective communication operations is the key to achieve high-performance parallel computing. But the heterogeneity of the system complicates the design. In this paper, we consider design of an efficient gather operation, one of the most important collective operations. We show that an optimal gather schedule is found in O(n^2k-1) time for the heterogeneous parallel computing environment with n processors of k distinct types, and that a nearly-optimal schedule is found in O(n) time if k=2.

This paper proposes an improvement of Elkies' point counting algorithm for the Jacobian of a genus 2 hyperelliptic curve defined over a finite field in a practical sense and introduces experimental results. Our experimental results show that we can generate a cryptographic secure genus 2 hyperelliptic curve, where the order of its Jacobian is a 160-bit prime number in about 8.1 minutes on average, on a 700 MHz PentiumIII level PC. We improve Elkies' algorithm by proposing some complementary techniques for speeding up the baby-step giant-step.

A parity check matrix for a binary linear code defines a bipartite graph (Tanner graph) which is isomorphic to a subgraph of a factor graph which explains a mechanism of the iterative decoding based on the sum-product algorithm. It is known that this decoding algorithm well approximates MAP decoding, but degradation of the approximation becomes serious when there exist cycles of short length, especially length 4, in Tanner graph. In this paper, based on the generating idempotents, we propose some methods to design parity check matrices for cyclic codes which define Tanner graphs with no cycles of length 4. We also show numerically error performance of cyclic codes by the iterative decoding implemented on factor graphs derived from the proposed parity check matrices.

This paper proposes a gradient ascent learning algorithm for the elastic net approach to the Traveling Salesman Problem (TSP). The learning model has two phases: an elastic net phase, and a gradient ascent phase. The elastic net phase is equivalent to gradient descent of an energy function, and leads to a local minimum of energy that represents a good solution to the problem. Once the elastic net gets stuck in local minima, the gradient ascent phase attempts to fill up the valley by modifying parameters in a gradient ascent direction of the energy function. Thus, these two phases are iterated until the elastic net gets out of local minima. We test the algorithm on many randomly generated travel salesman problems up to 100 cities. For all problems, the systems are shown to be capable of escaping from the elastic net local minima and generating shorter tour than the original elastic net.

In this letter, we propose a frequency domain active noise control system using the time difference simultaneous perturbation method. This method is an algorithm based on the simultaneous perturbation method which updates the coefficients of the noise control filter only by use of the error signal. The time difference simultaneous perturbation method updates the filter coefficients by using one kind of error signal, while the simultaneous perturbation method updates the filter coefficients by using two kinds of error signal. In the ANC systems, the time difference simultaneous perturbation method is superior because ANC systems cannot obtain two error signals at the same time. When this method is applied to ANC systems, the convergence speed can be increased to a maximum of twice that of the conventional method.

In this letter, we propose a new technique that reduces the computation time to derive the MEI coefficients in solving scattering problems by the Measured Equation of Invariance (MEI) methods. Methods that use the MEI technique spend most of the computation time in the integration process to derive the MEI coefficients. Moreover, in the conventional solution process, some repeated computation of metron fields to derive the MEI coefficients is included. To avoid the repeated operations and thus save computation time, we propose a matrix localization technique in computing the MEI coefficients. The time comparison for the computation of MEI coefficients of a cylinder and a sphere is given to verify the CPU time reduction of our new technique.

GPS receivers are susceptible to jamming by interference. This paper proposes a recurrent neural network (RNN) predictor for new application in GPS anti-jamming systems. Five types of narrowband jammers, i. e. AR process, continuous wave interference (CWI), multi-tone CWI, swept CWI, and pulsed CWI, are considered in order to emulate realistic conditions. As the observation noise of received signals is highly non-Gaussian, an RNN estimator with a nonlinear structure is employed to accurately predict the narrowband signals based on a real-time learning method. The node decoupled extended Kalman filter (NDEKF) algorithm is adopted to achieve better performance in terms of convergence rate and quality of solution while requiring less computation time and memory. We analyze the computational complexity and memory requirements of the NDEKF approach and compare them to the global extended Kalman filter (GEKF) training paradigm. Simulation results show that our proposed scheme achieves a superior performance to conventional linear/nonlinear predictors in terms of SNR improvement and mean squared prediction error (MSPE) while providing inherent protection against a broad class of interference environments.

A novel postprocessing algorithm for reducing the blocking artifacts in block-based coded images is proposed using block classification and adaptive multi-layer perceptron (MLP). This algorithm is exploited the nonlinearity property of the neural network learning algorithm to reduce the blocking artifacts more accurately. In this algorithm, each block is classified into four classes; smooth, horizontal edge, vertical edge, and complex blocks, based on the characteristic of their discrete cosine transform (DCT) coefficients. Thereafter, according to the class information of the neighborhood block, adaptive neural network filters (NNF) are then applied to the horizontal and vertical block boundaries. That is, for each class a different two-layer NNF is used to remove the blocking artifacts. Experimental results show that the proposed algorithm produced better results than conventional algorithms both subjectively and objectively.

We have classified parenchymal echo patterns of cirrhotic liver into four types, according to the size of hypo echoic nodular lesions. The NN (neural network) technique has been applied to the characterization of hepatic parenchymal diseases in ultrasonic B-scan texture. We employed a multilayer feedforward NN utilizing the back-propagation algorithm. We extracted 1616 pixels in the two-dimensional regions. However, when a large area is used, input data becomes large and much time is needed for diagnosis. In this report, we used DCT (discrete cosine transform) for the feature extraction of input data, and compression. As a result, DCT was found to be suitable for compressing ultrasonographic images.