Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality

Koji INOUE; Vasily G. MOSHNYAGA; Kazuaki MURAKAMI

Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality

Koji INOUE, Vasily G. MOSHNYAGA, Kazuaki MURAKAMI

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In this paper, we propose an instruction encoding scheme to reduce power consumption of instruction ROMs. The power consumption of the instruction ROM strongly depends on the switching activity of bit-lines due to their large load capacitance. In our approach, the binary-patterns to be assigned as op-codes are determined based on the frequency of instructions in order to reduce the number of bit-line dis-charging. Simulation results show that our approach can reduce 40% of bit-line switchings from a conventional organization.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.4 pp.799-805

Publication Date: 2003/04/01

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Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)

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Koji INOUE, Vasily G. MOSHNYAGA, Kazuaki MURAKAMI, "Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality" in IEICE TRANSACTIONS on Fundamentals, vol. E86-A, no. 4, pp. 799-805, April 2003, doi: .
Abstract: In this paper, we propose an instruction encoding scheme to reduce power consumption of instruction ROMs. The power consumption of the instruction ROM strongly depends on the switching activity of bit-lines due to their large load capacitance. In our approach, the binary-patterns to be assigned as op-codes are determined based on the frequency of instructions in order to reduce the number of bit-line dis-charging. Simulation results show that our approach can reduce 40% of bit-line switchings from a conventional organization.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e86-a_4_799/_p

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@ARTICLE{e86-a_4_799,
author={Koji INOUE, Vasily G. MOSHNYAGA, Kazuaki MURAKAMI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality},
year={2003},
volume={E86-A},
number={4},
pages={799-805},
abstract={In this paper, we propose an instruction encoding scheme to reduce power consumption of instruction ROMs. The power consumption of the instruction ROM strongly depends on the switching activity of bit-lines due to their large load capacitance. In our approach, the binary-patterns to be assigned as op-codes are determined based on the frequency of instructions in order to reduce the number of bit-line dis-charging. Simulation results show that our approach can reduce 40% of bit-line switchings from a conventional organization.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 799
EP - 805
AU - Koji INOUE
AU - Vasily G. MOSHNYAGA
AU - Kazuaki MURAKAMI
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2003
AB - In this paper, we propose an instruction encoding scheme to reduce power consumption of instruction ROMs. The power consumption of the instruction ROM strongly depends on the switching activity of bit-lines due to their large load capacitance. In our approach, the binary-patterns to be assigned as op-codes are determined based on the frequency of instructions in order to reduce the number of bit-line dis-charging. Simulation results show that our approach can reduce 40% of bit-line switchings from a conventional organization.
ER -