Power Analysis and Estimation for SOC Design: Techniques and Tools

Yun CAO; Hiroto YASUURA

Power Analysis and Estimation for SOC Design: Techniques and Tools

Yun CAO, Hiroto YASUURA

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As power consumption becoming a critical concern for System-On-a-Chip (SOC) design, accurate and efficient power analysis and estimation during the design phase at all levels of abstraction are becoming increasingly pressing in order to achieve low power without a costly redesign process. This paper surveys analysis and estimation techniques of dynamic power and leakage power for SOC design covering multiple design levels, which have been recently proposed, aiming to present a cohesive view of the power estimation techniques at all design levels of abstraction.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.2 pp.410-416

Publication Date: 2004/02/01

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Type of Manuscript: REVIEW PAPER

Category: VLSI Design Technology and CAD

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Yun CAO, Hiroto YASUURA, "Power Analysis and Estimation for SOC Design: Techniques and Tools" in IEICE TRANSACTIONS on Fundamentals, vol. E87-A, no. 2, pp. 410-416, February 2004, doi: .
Abstract: As power consumption becoming a critical concern for System-On-a-Chip (SOC) design, accurate and efficient power analysis and estimation during the design phase at all levels of abstraction are becoming increasingly pressing in order to achieve low power without a costly redesign process. This paper surveys analysis and estimation techniques of dynamic power and leakage power for SOC design covering multiple design levels, which have been recently proposed, aiming to present a cohesive view of the power estimation techniques at all design levels of abstraction.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e87-a_2_410/_p

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author={Yun CAO, Hiroto YASUURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Power Analysis and Estimation for SOC Design: Techniques and Tools},
year={2004},
volume={E87-A},
number={2},
pages={410-416},
abstract={As power consumption becoming a critical concern for System-On-a-Chip (SOC) design, accurate and efficient power analysis and estimation during the design phase at all levels of abstraction are becoming increasingly pressing in order to achieve low power without a costly redesign process. This paper surveys analysis and estimation techniques of dynamic power and leakage power for SOC design covering multiple design levels, which have been recently proposed, aiming to present a cohesive view of the power estimation techniques at all design levels of abstraction.},
keywords={},
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month={February},}

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TY - JOUR
TI - Power Analysis and Estimation for SOC Design: Techniques and Tools
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 410
EP - 416
AU - Yun CAO
AU - Hiroto YASUURA
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2004
AB - As power consumption becoming a critical concern for System-On-a-Chip (SOC) design, accurate and efficient power analysis and estimation during the design phase at all levels of abstraction are becoming increasingly pressing in order to achieve low power without a costly redesign process. This paper surveys analysis and estimation techniques of dynamic power and leakage power for SOC design covering multiple design levels, which have been recently proposed, aiming to present a cohesive view of the power estimation techniques at all design levels of abstraction.
ER -