Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model

Takuya KOMAWAKI; Michitarou YABUUCHI; Ryo KISHIDA; Jun FURUTA; Takashi MATSUMOTO; Kazutoshi KOBAYASHI

doi:10.1587/transfun.E100.A.2758

Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model

Takuya KOMAWAKI, Michitarou YABUUCHI, Ryo KISHIDA, Jun FURUTA, Takashi MATSUMOTO, Kazutoshi KOBAYASHI

Full Text Views

0

Share
Cite this

Summary :

As device sizes are downscaled to nanometer, Random Telegraph Noise (RTN) becomes dominant. It is indispensable to accurately estimate the effect of RTN. We propose an RTN simulation method for analog circuits. It is based on the charge trapping model. The RTN-induced threshold voltage fluctuation are replicated to attach a variable DC voltage source to the gate of a MOSFET by using Verilog-AMS. In recent deca-nanometer processes, high-k (HK) materials are used in gate dielectrics to decrease the leakage current. We must consider the defect distribution characteristics both in HK and interface layer (IL). This RTN model can be applied to the bimodal model which includes characteristics of the HK and IL dielectrics. We confirm that the drain current of MOSFETs temporally fluctuates in circuit-level simulations. The fluctuations of RTN are different in MOSFETs. RTN affects the frequency characteristics of ring oscillators (ROs). The distribution of RTN-induced frequency fluctuations has a long-tail in a HK process. The RTN model applied to the bimodal can replicate a long-tail distribution. Our proposed method can estimate the temporal impact of RTN including multiple transistors.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E100-A No.12 pp.2758-2763

Publication Date: 2017/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E100.A.2758

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category

Authors

Takuya KOMAWAKI
  Kyoto Institute of Technology
Michitarou YABUUCHI
  Kyoto Institute of Technology
Ryo KISHIDA
  Kyoto Institute of Technology
Jun FURUTA
  Kyoto Institute of Technology
Takashi MATSUMOTO
  The University of Tokyo
Kazutoshi KOBAYASHI
  Kyoto Institute of Technology

Keyword

Random Telegraph Noise, reliability, Verilog-AMS

Cite this

Copy

Takuya KOMAWAKI, Michitarou YABUUCHI, Ryo KISHIDA, Jun FURUTA, Takashi MATSUMOTO, Kazutoshi KOBAYASHI, "Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model" in IEICE TRANSACTIONS on Fundamentals, vol. E100-A, no. 12, pp. 2758-2763, December 2017, doi: 10.1587/transfun.E100.A.2758.
Abstract: As device sizes are downscaled to nanometer, Random Telegraph Noise (RTN) becomes dominant. It is indispensable to accurately estimate the effect of RTN. We propose an RTN simulation method for analog circuits. It is based on the charge trapping model. The RTN-induced threshold voltage fluctuation are replicated to attach a variable DC voltage source to the gate of a MOSFET by using Verilog-AMS. In recent deca-nanometer processes, high-k (HK) materials are used in gate dielectrics to decrease the leakage current. We must consider the defect distribution characteristics both in HK and interface layer (IL). This RTN model can be applied to the bimodal model which includes characteristics of the HK and IL dielectrics. We confirm that the drain current of MOSFETs temporally fluctuates in circuit-level simulations. The fluctuations of RTN are different in MOSFETs. RTN affects the frequency characteristics of ring oscillators (ROs). The distribution of RTN-induced frequency fluctuations has a long-tail in a HK process. The RTN model applied to the bimodal can replicate a long-tail distribution. Our proposed method can estimate the temporal impact of RTN including multiple transistors.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E100.A.2758/_p

Copy

@ARTICLE{e100-a_12_2758,
author={Takuya KOMAWAKI, Michitarou YABUUCHI, Ryo KISHIDA, Jun FURUTA, Takashi MATSUMOTO, Kazutoshi KOBAYASHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model},
year={2017},
volume={E100-A},
number={12},
pages={2758-2763},
abstract={As device sizes are downscaled to nanometer, Random Telegraph Noise (RTN) becomes dominant. It is indispensable to accurately estimate the effect of RTN. We propose an RTN simulation method for analog circuits. It is based on the charge trapping model. The RTN-induced threshold voltage fluctuation are replicated to attach a variable DC voltage source to the gate of a MOSFET by using Verilog-AMS. In recent deca-nanometer processes, high-k (HK) materials are used in gate dielectrics to decrease the leakage current. We must consider the defect distribution characteristics both in HK and interface layer (IL). This RTN model can be applied to the bimodal model which includes characteristics of the HK and IL dielectrics. We confirm that the drain current of MOSFETs temporally fluctuates in circuit-level simulations. The fluctuations of RTN are different in MOSFETs. RTN affects the frequency characteristics of ring oscillators (ROs). The distribution of RTN-induced frequency fluctuations has a long-tail in a HK process. The RTN model applied to the bimodal can replicate a long-tail distribution. Our proposed method can estimate the temporal impact of RTN including multiple transistors.},
keywords={},
doi={10.1587/transfun.E100.A.2758},
ISSN={1745-1337},
month={December},}

Copy

TY - JOUR
TI - Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2758
EP - 2763
AU - Takuya KOMAWAKI
AU - Michitarou YABUUCHI
AU - Ryo KISHIDA
AU - Jun FURUTA
AU - Takashi MATSUMOTO
AU - Kazutoshi KOBAYASHI
PY - 2017
DO - 10.1587/transfun.E100.A.2758
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E100-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2017
AB - As device sizes are downscaled to nanometer, Random Telegraph Noise (RTN) becomes dominant. It is indispensable to accurately estimate the effect of RTN. We propose an RTN simulation method for analog circuits. It is based on the charge trapping model. The RTN-induced threshold voltage fluctuation are replicated to attach a variable DC voltage source to the gate of a MOSFET by using Verilog-AMS. In recent deca-nanometer processes, high-k (HK) materials are used in gate dielectrics to decrease the leakage current. We must consider the defect distribution characteristics both in HK and interface layer (IL). This RTN model can be applied to the bimodal model which includes characteristics of the HK and IL dielectrics. We confirm that the drain current of MOSFETs temporally fluctuates in circuit-level simulations. The fluctuations of RTN are different in MOSFETs. RTN affects the frequency characteristics of ring oscillators (ROs). The distribution of RTN-induced frequency fluctuations has a long-tail in a HK process. The RTN model applied to the bimodal can replicate a long-tail distribution. Our proposed method can estimate the temporal impact of RTN including multiple transistors.
ER -