An Inductive-Coupling Interconnected Application-Specific 3D NoC Design

Zhen ZHANG; Shouyi YIN; Leibo LIU; Shaojun WEI

doi:10.1587/transfun.E96.A.2633

An Inductive-Coupling Interconnected Application-Specific 3D NoC Design

Zhen ZHANG, Shouyi YIN, Leibo LIU, Shaojun WEI

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Summary :

TSV-interconnected 3D chips face problems such as high cost, low yield and large power dissipation. We propose a wireless 3D on-chip-network architecture for application-specific SoC design, using inductive-coupling interconnect instead of TSV for inter-layer communication. Primary design challenge of inductive-coupling 3D SoC is allocating wireless links in the 3D on-chip network effectively. We develop a design flow fully exploiting the design space brought by wireless links while providing flexible tradeoff for user's choice. Experimental results show that our design brings great improvement over uniform design and Sunfloor algorithm on latency (5% to 20%) and power consumption (10% to 45%).

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.12 pp.2633-2644

Publication Date: 2013/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E96.A.2633

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: High-Level Synthesis and System-Level Design

Authors

Zhen ZHANG
  Tsinghua University
Shouyi YIN
  Tsinghua University
Leibo LIU
  Tsinghua University
Shaojun WEI
  Tsinghua University

Keyword

Networks-on-Chip (NoC), 3D chip, inductive-coupling interconnection, design automation

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Zhen ZHANG, Shouyi YIN, Leibo LIU, Shaojun WEI, "An Inductive-Coupling Interconnected Application-Specific 3D NoC Design" in IEICE TRANSACTIONS on Fundamentals, vol. E96-A, no. 12, pp. 2633-2644, December 2013, doi: 10.1587/transfun.E96.A.2633.
Abstract: TSV-interconnected 3D chips face problems such as high cost, low yield and large power dissipation. We propose a wireless 3D on-chip-network architecture for application-specific SoC design, using inductive-coupling interconnect instead of TSV for inter-layer communication. Primary design challenge of inductive-coupling 3D SoC is allocating wireless links in the 3D on-chip network effectively. We develop a design flow fully exploiting the design space brought by wireless links while providing flexible tradeoff for user's choice. Experimental results show that our design brings great improvement over uniform design and Sunfloor algorithm on latency (5% to 20%) and power consumption (10% to 45%).
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.2633/_p

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@ARTICLE{e96-a_12_2633,
author={Zhen ZHANG, Shouyi YIN, Leibo LIU, Shaojun WEI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Inductive-Coupling Interconnected Application-Specific 3D NoC Design},
year={2013},
volume={E96-A},
number={12},
pages={2633-2644},
abstract={TSV-interconnected 3D chips face problems such as high cost, low yield and large power dissipation. We propose a wireless 3D on-chip-network architecture for application-specific SoC design, using inductive-coupling interconnect instead of TSV for inter-layer communication. Primary design challenge of inductive-coupling 3D SoC is allocating wireless links in the 3D on-chip network effectively. We develop a design flow fully exploiting the design space brought by wireless links while providing flexible tradeoff for user's choice. Experimental results show that our design brings great improvement over uniform design and Sunfloor algorithm on latency (5% to 20%) and power consumption (10% to 45%).},
keywords={},
doi={10.1587/transfun.E96.A.2633},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - An Inductive-Coupling Interconnected Application-Specific 3D NoC Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2633
EP - 2644
AU - Zhen ZHANG
AU - Shouyi YIN
AU - Leibo LIU
AU - Shaojun WEI
PY - 2013
DO - 10.1587/transfun.E96.A.2633
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2013
AB - TSV-interconnected 3D chips face problems such as high cost, low yield and large power dissipation. We propose a wireless 3D on-chip-network architecture for application-specific SoC design, using inductive-coupling interconnect instead of TSV for inter-layer communication. Primary design challenge of inductive-coupling 3D SoC is allocating wireless links in the 3D on-chip network effectively. We develop a design flow fully exploiting the design space brought by wireless links while providing flexible tradeoff for user's choice. Experimental results show that our design brings great improvement over uniform design and Sunfloor algorithm on latency (5% to 20%) and power consumption (10% to 45%).
ER -