A 4–10 bit, 0.4–1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller

Akira SHIKATA; Ryota SEKIMOTO; Kentaro YOSHIOKA; Tadahiro KURODA; Hiroki ISHIKURO

doi:10.1587/transfun.E96.A.443

A 4–10 bit, 0.4–1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller

Akira SHIKATA, Ryota SEKIMOTO, Kentaro YOSHIOKA, Tadahiro KURODA, Hiroki ISHIKURO

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This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed differential flip-flop in SAR logic and high efficiency wide range delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 40 nm CMOS process covers 4–10 bit resolution and 0.4–1 V power supply range. The ADC achieved 49.8 dB SNDR and the peak FoM of 3.4 fJ/conv. with 160 kS/sec at 0.4 V single power supply voltage. At 10 bit mode and 1 V operation, up to 10 MS/s, the FoM is below 10 fJ/conv. while keeping ENOB of 8.7 bit.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.2 pp.443-452

Publication Date: 2013/02/01

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Online ISSN: 1745-1337

DOI: 10.1587/transfun.E96.A.443

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)

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Akira SHIKATA, Ryota SEKIMOTO, Kentaro YOSHIOKA, Tadahiro KURODA, Hiroki ISHIKURO, "A 4–10 bit, 0.4–1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller" in IEICE TRANSACTIONS on Fundamentals, vol. E96-A, no. 2, pp. 443-452, February 2013, doi: 10.1587/transfun.E96.A.443.
Abstract: This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed differential flip-flop in SAR logic and high efficiency wide range delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 40 nm CMOS process covers 4–10 bit resolution and 0.4–1 V power supply range. The ADC achieved 49.8 dB SNDR and the peak FoM of 3.4 fJ/conv. with 160 kS/sec at 0.4 V single power supply voltage. At 10 bit mode and 1 V operation, up to 10 MS/s, the FoM is below 10 fJ/conv. while keeping ENOB of 8.7 bit.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.443/_p

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@ARTICLE{e96-a_2_443,
author={Akira SHIKATA, Ryota SEKIMOTO, Kentaro YOSHIOKA, Tadahiro KURODA, Hiroki ISHIKURO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 4–10 bit, 0.4–1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller},
year={2013},
volume={E96-A},
number={2},
pages={443-452},
abstract={This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed differential flip-flop in SAR logic and high efficiency wide range delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 40 nm CMOS process covers 4–10 bit resolution and 0.4–1 V power supply range. The ADC achieved 49.8 dB SNDR and the peak FoM of 3.4 fJ/conv. with 160 kS/sec at 0.4 V single power supply voltage. At 10 bit mode and 1 V operation, up to 10 MS/s, the FoM is below 10 fJ/conv. while keeping ENOB of 8.7 bit.},
keywords={},
doi={10.1587/transfun.E96.A.443},
ISSN={1745-1337},
month={February},}

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TY - JOUR
TI - A 4–10 bit, 0.4–1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 443
EP - 452
AU - Akira SHIKATA
AU - Ryota SEKIMOTO
AU - Kentaro YOSHIOKA
AU - Tadahiro KURODA
AU - Hiroki ISHIKURO
PY - 2013
DO - 10.1587/transfun.E96.A.443
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2013
AB - This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed differential flip-flop in SAR logic and high efficiency wide range delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 40 nm CMOS process covers 4–10 bit resolution and 0.4–1 V power supply range. The ADC achieved 49.8 dB SNDR and the peak FoM of 3.4 fJ/conv. with 160 kS/sec at 0.4 V single power supply voltage. At 10 bit mode and 1 V operation, up to 10 MS/s, the FoM is below 10 fJ/conv. while keeping ENOB of 8.7 bit.
ER -