Design and Implement of High Performance Crypto Coprocessor

Shice NI; Yong DOU; Kai CHEN; Jie ZHOU

doi:10.1587/transfun.E97.A.989

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Shice NI, Yong DOU, Kai CHEN, Jie ZHOU, "Design and Implement of High Performance Crypto Coprocessor" in IEICE TRANSACTIONS on Fundamentals, vol. E97-A, no. 4, pp. 989-990, April 2014, doi: 10.1587/transfun.E97.A.989.
Abstract: This letter proposes a novel high performance crypto coprocessor that relies on Reconfigurable Cryptographic Blocks. We implement the prototype of the coprocessor on Xilinx FPGA chip. And the pipelining technique is adopted to realize data paralleling. The results show that the coprocessor, running at 189MHz, outperforms the software-based SSL protocol.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E97.A.989/_p

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@ARTICLE{e97-a_4_989,
author={Shice NI, Yong DOU, Kai CHEN, Jie ZHOU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design and Implement of High Performance Crypto Coprocessor},
year={2014},
volume={E97-A},
number={4},
pages={989-990},
abstract={This letter proposes a novel high performance crypto coprocessor that relies on Reconfigurable Cryptographic Blocks. We implement the prototype of the coprocessor on Xilinx FPGA chip. And the pipelining technique is adopted to realize data paralleling. The results show that the coprocessor, running at 189MHz, outperforms the software-based SSL protocol.},
keywords={},
doi={10.1587/transfun.E97.A.989},
ISSN={1745-1337},
month={April},}

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TY - JOUR
TI - Design and Implement of High Performance Crypto Coprocessor
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 989
EP - 990
AU - Shice NI
AU - Yong DOU
AU - Kai CHEN
AU - Jie ZHOU
PY - 2014
DO - 10.1587/transfun.E97.A.989
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E97-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2014
AB - This letter proposes a novel high performance crypto coprocessor that relies on Reconfigurable Cryptographic Blocks. We implement the prototype of the coprocessor on Xilinx FPGA chip. And the pipelining technique is adopted to realize data paralleling. The results show that the coprocessor, running at 189MHz, outperforms the software-based SSL protocol.
ER -