Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell

Mitsutoshi SUGAWARA; Kenji MORI; Zule XU; Masaya MIYAHARA; Kenichi OKADA; Akira MATSUZAWA

doi:10.1587/transfun.E99.A.2435

Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell

Mitsutoshi SUGAWARA, Kenji MORI, Zule XU, Masaya MIYAHARA, Kenichi OKADA, Akira MATSUZAWA

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We propose a synthesis and automatic layout method for mixed-signal circuits with high regularity. As the first step of this research, a resistive digital-to-analog converter (RDAC) is presented. With a size calculation routine, the area of this RDAC is minimized while satisfying the required matching precision without any optimization loops. We propose to partition the design into slices comprising of both analog and digital cells. These cells are programmed to be synthesized as similar as custom P-Cells based on the calculation above, and automatically laid out to form one slice cell. To synthesize digital circuits, without using digital standard cell library, we propose a versatile unit digital block consisting of 8 transistors. With one or several blocks, the transistors' interconnections are programmed in the units to realize various logic gates. By using this block, the slice shapes are aligned so that the layout space in between the slices are minimized. The proposed mixed-signal slice-based partition facilitates the place-and-route of the whole RDAC. The post-layout simulation shows that the generated 9-bit RDAC achieves 1GHz sampling frequency, -0.11/0.09 and -0.30/0.75 DNL and INL, respectively, 3.57mW power consumption, and 0.0038mm² active area.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E99-A No.12 pp.2435-2443

Publication Date: 2016/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E99.A.2435

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

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Authors

Mitsutoshi SUGAWARA
  Tokyo Institute of Technology
Kenji MORI
  Tokyo Institute of Technology
Zule XU
  Tokyo Institute of Technology
Masaya MIYAHARA
  Tokyo Institute of Technology
Kenichi OKADA
  Tokyo Institute of Technology
Akira MATSUZAWA
  Tokyo Institute of Technology

Keyword

analog synthesis, RDAC, slice-based layout, SKILL language

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Mitsutoshi SUGAWARA, Kenji MORI, Zule XU, Masaya MIYAHARA, Kenichi OKADA, Akira MATSUZAWA, "Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell" in IEICE TRANSACTIONS on Fundamentals, vol. E99-A, no. 12, pp. 2435-2443, December 2016, doi: 10.1587/transfun.E99.A.2435.
Abstract: We propose a synthesis and automatic layout method for mixed-signal circuits with high regularity. As the first step of this research, a resistive digital-to-analog converter (RDAC) is presented. With a size calculation routine, the area of this RDAC is minimized while satisfying the required matching precision without any optimization loops. We propose to partition the design into slices comprising of both analog and digital cells. These cells are programmed to be synthesized as similar as custom P-Cells based on the calculation above, and automatically laid out to form one slice cell. To synthesize digital circuits, without using digital standard cell library, we propose a versatile unit digital block consisting of 8 transistors. With one or several blocks, the transistors' interconnections are programmed in the units to realize various logic gates. By using this block, the slice shapes are aligned so that the layout space in between the slices are minimized. The proposed mixed-signal slice-based partition facilitates the place-and-route of the whole RDAC. The post-layout simulation shows that the generated 9-bit RDAC achieves 1GHz sampling frequency, -0.11/0.09 and -0.30/0.75 DNL and INL, respectively, 3.57mW power consumption, and 0.0038mm² active area.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E99.A.2435/_p

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@ARTICLE{e99-a_12_2435,
author={Mitsutoshi SUGAWARA, Kenji MORI, Zule XU, Masaya MIYAHARA, Kenichi OKADA, Akira MATSUZAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell},
year={2016},
volume={E99-A},
number={12},
pages={2435-2443},
abstract={We propose a synthesis and automatic layout method for mixed-signal circuits with high regularity. As the first step of this research, a resistive digital-to-analog converter (RDAC) is presented. With a size calculation routine, the area of this RDAC is minimized while satisfying the required matching precision without any optimization loops. We propose to partition the design into slices comprising of both analog and digital cells. These cells are programmed to be synthesized as similar as custom P-Cells based on the calculation above, and automatically laid out to form one slice cell. To synthesize digital circuits, without using digital standard cell library, we propose a versatile unit digital block consisting of 8 transistors. With one or several blocks, the transistors' interconnections are programmed in the units to realize various logic gates. By using this block, the slice shapes are aligned so that the layout space in between the slices are minimized. The proposed mixed-signal slice-based partition facilitates the place-and-route of the whole RDAC. The post-layout simulation shows that the generated 9-bit RDAC achieves 1GHz sampling frequency, -0.11/0.09 and -0.30/0.75 DNL and INL, respectively, 3.57mW power consumption, and 0.0038mm² active area.},
keywords={},
doi={10.1587/transfun.E99.A.2435},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2435
EP - 2443
AU - Mitsutoshi SUGAWARA
AU - Kenji MORI
AU - Zule XU
AU - Masaya MIYAHARA
AU - Kenichi OKADA
AU - Akira MATSUZAWA
PY - 2016
DO - 10.1587/transfun.E99.A.2435
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E99-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2016
AB - We propose a synthesis and automatic layout method for mixed-signal circuits with high regularity. As the first step of this research, a resistive digital-to-analog converter (RDAC) is presented. With a size calculation routine, the area of this RDAC is minimized while satisfying the required matching precision without any optimization loops. We propose to partition the design into slices comprising of both analog and digital cells. These cells are programmed to be synthesized as similar as custom P-Cells based on the calculation above, and automatically laid out to form one slice cell. To synthesize digital circuits, without using digital standard cell library, we propose a versatile unit digital block consisting of 8 transistors. With one or several blocks, the transistors' interconnections are programmed in the units to realize various logic gates. By using this block, the slice shapes are aligned so that the layout space in between the slices are minimized. The proposed mixed-signal slice-based partition facilitates the place-and-route of the whole RDAC. The post-layout simulation shows that the generated 9-bit RDAC achieves 1GHz sampling frequency, -0.11/0.09 and -0.30/0.75 DNL and INL, respectively, 3.57mW power consumption, and 0.0038mm² active area.
ER -