Design and Evaluation of Hardware Pseudo-Random Number Generator MT19937

Shiro KONUMA; Shuichi ICHIKAWA

doi:10.1093/ietisy/e88-d.12.2876

Design and Evaluation of Hardware Pseudo-Random Number Generator MT19937

Shiro KONUMA, Shuichi ICHIKAWA

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MT19937 is a kind of Mersenne Twister, which is a pseudo-random number generator. This study presents new designs for a MT19937 circuit suitable for custom computing machinery for high-performance scientific simulations. Our designs can generate multiple random numbers per cycle (multi-port design). The estimated throughput of a 52-port design was 262 Gbps, which is 115 times higher than the software on a Pentium 4 (2.53 GHz) processor. Multi-port designs were proven to be more cost-effective than using multiple single-port designs. The initialization circuit can be included without performance loss in exchange for a slight increase of logic scale.

Publication: IEICE TRANSACTIONS on Information Vol.E88-D No.12 pp.2876-2879

Publication Date: 2005/12/01

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Online ISSN

DOI: 10.1093/ietisy/e88-d.12.2876

Type of Manuscript: LETTER

Category: VLSI Systems

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Shiro KONUMA, Shuichi ICHIKAWA, "Design and Evaluation of Hardware Pseudo-Random Number Generator MT19937" in IEICE TRANSACTIONS on Information, vol. E88-D, no. 12, pp. 2876-2879, December 2005, doi: 10.1093/ietisy/e88-d.12.2876.
Abstract: MT19937 is a kind of Mersenne Twister, which is a pseudo-random number generator. This study presents new designs for a MT19937 circuit suitable for custom computing machinery for high-performance scientific simulations. Our designs can generate multiple random numbers per cycle (multi-port design). The estimated throughput of a 52-port design was 262 Gbps, which is 115 times higher than the software on a Pentium 4 (2.53 GHz) processor. Multi-port designs were proven to be more cost-effective than using multiple single-port designs. The initialization circuit can be included without performance loss in exchange for a slight increase of logic scale.
URL: https://globals.ieice.org/en_transactions/information/10.1093/ietisy/e88-d.12.2876/_p

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@ARTICLE{e88-d_12_2876,
author={Shiro KONUMA, Shuichi ICHIKAWA, },
journal={IEICE TRANSACTIONS on Information},
title={Design and Evaluation of Hardware Pseudo-Random Number Generator MT19937},
year={2005},
volume={E88-D},
number={12},
pages={2876-2879},
abstract={MT19937 is a kind of Mersenne Twister, which is a pseudo-random number generator. This study presents new designs for a MT19937 circuit suitable for custom computing machinery for high-performance scientific simulations. Our designs can generate multiple random numbers per cycle (multi-port design). The estimated throughput of a 52-port design was 262 Gbps, which is 115 times higher than the software on a Pentium 4 (2.53 GHz) processor. Multi-port designs were proven to be more cost-effective than using multiple single-port designs. The initialization circuit can be included without performance loss in exchange for a slight increase of logic scale.},
keywords={},
doi={10.1093/ietisy/e88-d.12.2876},
ISSN={},
month={December},}

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TY - JOUR
TI - Design and Evaluation of Hardware Pseudo-Random Number Generator MT19937
T2 - IEICE TRANSACTIONS on Information
SP - 2876
EP - 2879
AU - Shiro KONUMA
AU - Shuichi ICHIKAWA
PY - 2005
DO - 10.1093/ietisy/e88-d.12.2876
JO - IEICE TRANSACTIONS on Information
SN -
VL - E88-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2005
AB - MT19937 is a kind of Mersenne Twister, which is a pseudo-random number generator. This study presents new designs for a MT19937 circuit suitable for custom computing machinery for high-performance scientific simulations. Our designs can generate multiple random numbers per cycle (multi-port design). The estimated throughput of a 52-port design was 262 Gbps, which is 115 times higher than the software on a Pentium 4 (2.53 GHz) processor. Multi-port designs were proven to be more cost-effective than using multiple single-port designs. The initialization circuit can be included without performance loss in exchange for a slight increase of logic scale.
ER -