Experimental Study of Jitter Effect on Digital Downconversion Receiver with Undersampling Scheme

Minseok KIM; Aiko KIYONO; Koichi ICHIGE; Hiroyuki ARAI

doi:10.1093/ietisy/e88-d.7.1430

Experimental Study of Jitter Effect on Digital Downconversion Receiver with Undersampling Scheme

Minseok KIM, Aiko KIYONO, Koichi ICHIGE, Hiroyuki ARAI

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Undersampling (or bandpass sampling) phase modulated signals directly at high frequency band, the harmful effects of the aperture jitter characteristics of ADCs (Analog-to-Digital converters) and sampling clock instability of the system can not be ignored. In communication systems the sampling jitter brings additional phase noise to the constellation pattern besides thermal noise, thus the BER (bit error rate) performance will be degraded. This paper examines the relationship between the input frequency to ADC and the sampling jitter in digital IF (Intermediate Frequency) downconversion receivers with undersampling scheme. This paper presents the measurement results with a real hardware prototype system as well as the computer simulation results with a theoretically modeled IF sampling receiver. We evaluated EVM (Error Vector Magnitude) in various clock jitter configurations with commonly used and reasonable cost ADCs of which sampling rates was 40 MHz. According to the results, the IF input frequencies of QPSK (16 QAM) signals were limited below around 290 (210) MHz for wireless LAN standard, and 730 (450) MHz for W-CDMA standard, respectively, in our best configuration.

Publication: IEICE TRANSACTIONS on Information Vol.E88-D No.7 pp.1430-1436

Publication Date: 2005/07/01

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DOI: 10.1093/ietisy/e88-d.7.1430

Type of Manuscript: Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)

Category: Communications and Wireless Systems

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Minseok KIM, Aiko KIYONO, Koichi ICHIGE, Hiroyuki ARAI, "Experimental Study of Jitter Effect on Digital Downconversion Receiver with Undersampling Scheme" in IEICE TRANSACTIONS on Information, vol. E88-D, no. 7, pp. 1430-1436, July 2005, doi: 10.1093/ietisy/e88-d.7.1430.
Abstract: Undersampling (or bandpass sampling) phase modulated signals directly at high frequency band, the harmful effects of the aperture jitter characteristics of ADCs (Analog-to-Digital converters) and sampling clock instability of the system can not be ignored. In communication systems the sampling jitter brings additional phase noise to the constellation pattern besides thermal noise, thus the BER (bit error rate) performance will be degraded. This paper examines the relationship between the input frequency to ADC and the sampling jitter in digital IF (Intermediate Frequency) downconversion receivers with undersampling scheme. This paper presents the measurement results with a real hardware prototype system as well as the computer simulation results with a theoretically modeled IF sampling receiver. We evaluated EVM (Error Vector Magnitude) in various clock jitter configurations with commonly used and reasonable cost ADCs of which sampling rates was 40 MHz. According to the results, the IF input frequencies of QPSK (16 QAM) signals were limited below around 290 (210) MHz for wireless LAN standard, and 730 (450) MHz for W-CDMA standard, respectively, in our best configuration.
URL: https://globals.ieice.org/en_transactions/information/10.1093/ietisy/e88-d.7.1430/_p

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@ARTICLE{e88-d_7_1430,
author={Minseok KIM, Aiko KIYONO, Koichi ICHIGE, Hiroyuki ARAI, },
journal={IEICE TRANSACTIONS on Information},
title={Experimental Study of Jitter Effect on Digital Downconversion Receiver with Undersampling Scheme},
year={2005},
volume={E88-D},
number={7},
pages={1430-1436},
abstract={Undersampling (or bandpass sampling) phase modulated signals directly at high frequency band, the harmful effects of the aperture jitter characteristics of ADCs (Analog-to-Digital converters) and sampling clock instability of the system can not be ignored. In communication systems the sampling jitter brings additional phase noise to the constellation pattern besides thermal noise, thus the BER (bit error rate) performance will be degraded. This paper examines the relationship between the input frequency to ADC and the sampling jitter in digital IF (Intermediate Frequency) downconversion receivers with undersampling scheme. This paper presents the measurement results with a real hardware prototype system as well as the computer simulation results with a theoretically modeled IF sampling receiver. We evaluated EVM (Error Vector Magnitude) in various clock jitter configurations with commonly used and reasonable cost ADCs of which sampling rates was 40 MHz. According to the results, the IF input frequencies of QPSK (16 QAM) signals were limited below around 290 (210) MHz for wireless LAN standard, and 730 (450) MHz for W-CDMA standard, respectively, in our best configuration.},
keywords={},
doi={10.1093/ietisy/e88-d.7.1430},
ISSN={},
month={July},}

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TY - JOUR
TI - Experimental Study of Jitter Effect on Digital Downconversion Receiver with Undersampling Scheme
T2 - IEICE TRANSACTIONS on Information
SP - 1430
EP - 1436
AU - Minseok KIM
AU - Aiko KIYONO
AU - Koichi ICHIGE
AU - Hiroyuki ARAI
PY - 2005
DO - 10.1093/ietisy/e88-d.7.1430
JO - IEICE TRANSACTIONS on Information
SN -
VL - E88-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2005
AB - Undersampling (or bandpass sampling) phase modulated signals directly at high frequency band, the harmful effects of the aperture jitter characteristics of ADCs (Analog-to-Digital converters) and sampling clock instability of the system can not be ignored. In communication systems the sampling jitter brings additional phase noise to the constellation pattern besides thermal noise, thus the BER (bit error rate) performance will be degraded. This paper examines the relationship between the input frequency to ADC and the sampling jitter in digital IF (Intermediate Frequency) downconversion receivers with undersampling scheme. This paper presents the measurement results with a real hardware prototype system as well as the computer simulation results with a theoretically modeled IF sampling receiver. We evaluated EVM (Error Vector Magnitude) in various clock jitter configurations with commonly used and reasonable cost ADCs of which sampling rates was 40 MHz. According to the results, the IF input frequencies of QPSK (16 QAM) signals were limited below around 290 (210) MHz for wireless LAN standard, and 730 (450) MHz for W-CDMA standard, respectively, in our best configuration.
ER -