A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST

Youbean KIM; Kicheol KIM; Incheol KIM; Hyunwook SON; Sungho KANG

doi:10.1093/ietisy/e91-d.4.1185

A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST

Youbean KIM, Kicheol KIM, Incheol KIM, Hyunwook SON, Sungho KANG

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This paper presents a new low power BIST TPG scheme for reducing scan transitions. It uses a transition freezing and melting method which is implemented of the transition freezing block and a MUX. When random test patterns are generated from an LFSR, transitions of those patterns satisfy pseudo-random Gaussian distribution. The proposed technique freezes transitions of patterns using a freezing value. Experimental results show that the proposed BIST TPG schemes can reduce average power reduction by about 60% without performance loss and peak power by about 30% in ISCAS'89 benchmark circuits.

Publication: IEICE TRANSACTIONS on Information Vol.E91-D No.4 pp.1185-1188

Publication Date: 2008/04/01

Publicized

Online ISSN: 1745-1361

DOI: 10.1093/ietisy/e91-d.4.1185

Type of Manuscript: LETTER

Category: Computer Components

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Youbean KIM, Kicheol KIM, Incheol KIM, Hyunwook SON, Sungho KANG, "A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST" in IEICE TRANSACTIONS on Information, vol. E91-D, no. 4, pp. 1185-1188, April 2008, doi: 10.1093/ietisy/e91-d.4.1185.
Abstract: This paper presents a new low power BIST TPG scheme for reducing scan transitions. It uses a transition freezing and melting method which is implemented of the transition freezing block and a MUX. When random test patterns are generated from an LFSR, transitions of those patterns satisfy pseudo-random Gaussian distribution. The proposed technique freezes transitions of patterns using a freezing value. Experimental results show that the proposed BIST TPG schemes can reduce average power reduction by about 60% without performance loss and peak power by about 30% in ISCAS'89 benchmark circuits.
URL: https://globals.ieice.org/en_transactions/information/10.1093/ietisy/e91-d.4.1185/_p

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@ARTICLE{e91-d_4_1185,
author={Youbean KIM, Kicheol KIM, Incheol KIM, Hyunwook SON, Sungho KANG, },
journal={IEICE TRANSACTIONS on Information},
title={A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST},
year={2008},
volume={E91-D},
number={4},
pages={1185-1188},
abstract={This paper presents a new low power BIST TPG scheme for reducing scan transitions. It uses a transition freezing and melting method which is implemented of the transition freezing block and a MUX. When random test patterns are generated from an LFSR, transitions of those patterns satisfy pseudo-random Gaussian distribution. The proposed technique freezes transitions of patterns using a freezing value. Experimental results show that the proposed BIST TPG schemes can reduce average power reduction by about 60% without performance loss and peak power by about 30% in ISCAS'89 benchmark circuits.},
keywords={},
doi={10.1093/ietisy/e91-d.4.1185},
ISSN={1745-1361},
month={April},}

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TY - JOUR
TI - A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST
T2 - IEICE TRANSACTIONS on Information
SP - 1185
EP - 1188
AU - Youbean KIM
AU - Kicheol KIM
AU - Incheol KIM
AU - Hyunwook SON
AU - Sungho KANG
PY - 2008
DO - 10.1093/ietisy/e91-d.4.1185
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E91-D
IS - 4
JA - IEICE TRANSACTIONS on Information
Y1 - April 2008
AB - This paper presents a new low power BIST TPG scheme for reducing scan transitions. It uses a transition freezing and melting method which is implemented of the transition freezing block and a MUX. When random test patterns are generated from an LFSR, transitions of those patterns satisfy pseudo-random Gaussian distribution. The proposed technique freezes transitions of patterns using a freezing value. Experimental results show that the proposed BIST TPG schemes can reduce average power reduction by about 60% without performance loss and peak power by about 30% in ISCAS'89 benchmark circuits.
ER -