This paper presents a selective scan slice grouping technique for test data compression. In conventional selective encoding methods, the existence of a conflict bit contributes to large encoding data. However, many conflict bits are efficiently removed using the scan slice grouping technique, which leads to a dramatic improvement of encoding efficiency. Experiments performed with large ITC'99 benchmark circuits presents the effectiveness of the proposed technique and the test data volume is reduced up to 92% compared to random-filled test patterns.

In order to provide an efficient test method for PLL which is a mixed-signal circuit widely used in most of SoCs, a novel BIST method is developed. The new BIST uses the change of phase differences generated by selectively alternating the feedback frequency. It provides an efficient structural test, reduces an area overhead and improves the test accessibility.

This paper proposes a new BIST (Built-In Self-Test) method for static testing of an ADC (Analog-to-Digital Converter) with transition detection method. The proposed BIST uses a triangle-wave as an input test stimulus and calculates the ADC's static parameters. Simulation results show that the proposed BIST can test both rising and falling transitions with minimal hardware overhead.

This letter proposes a fast IP address lookup algorithm based on search space reduction. Prefixes are classified into three types according to the nesting relationship and a large forwarding table is partitioned into multiple small trees. As a result, the search space is reduced. The results of analyses and experiments show that the proposed method offers higher lookup and updating speeds along with reduced memory requirements.

This paper presents a grouped scan slice encoding technique using scan slice repetition to simultaneously reduce test data volume and test application time. Using this method, many scan slices that would be incompatible with the conventional selective scan slice method can be encoded as compatible scan slices. Experiments were performed with ISCAS'89 and ITC'99 benchmark circuits, and results show the effectiveness of the proposed method.

In this paper, we propose a new clustered reconfigurable interconnect network (CRIN) BIST that can improve the embedding probabilities of random-pattern-resistant-patterns. A simulated annealing based algorithm that maximizes the embedding probabilities of scan test cubes has been developed to reorder scan cells. Experimental results demonstrate that the proposed CRIN BIST technique reduces test time by 35% and the storage requirement by 39% in comparison with previous work.

This paper proposes a micro-code based Programmable Memory BIST (PMBIST) architecture that can support various kinds of test algorithms. The proposed Non-linear PMBIST (NPMBIST) guarantees high flexibility and high fault coverage using not only March algorithms but also non-linear algorithms such as Walking and Galloping. This NPMBIST has an optimized hardware overhead, since algorithms can be implemented with the minimum bits by the optimized instructions. Finally, various and complex algorithms can be run thanks to its support of multi-loop.

A new BIST (Built-in Self-test) method for static ADC testing is proposed. The proposed method detects offset, gain, INL (Integral Non-linearity) and DNL (Differential Non-linearity) errors with a low hardware overhead. Moreover, it can solve a transient zone problem which is derived from the ADC noise in real test environments.

To accomplish an efficient test pattern generation, the isomorphism identification algorithm and the pseudo dominator identification algorithm are developed which are used to identify redundant faults efficiently. Results show that test pattern generation using these algorithms is very efficient.

This paper presents a new low power BIST TPG scheme for reducing scan transitions. It uses a transition freezing and melting method which is implemented of the transition freezing block and a MUX. When random test patterns are generated from an LFSR, transitions of those patterns satisfy pseudo-random Gaussian distribution. The proposed technique freezes transitions of patterns using a freezing value. Experimental results show that the proposed BIST TPG schemes can reduce average power reduction by about 60% without performance loss and peak power by about 30% in ISCAS'89 benchmark circuits.

This paper presents a DFT controller called as a TCU (Test Control Unit), which considerably improves the efficiency of the instruction-based functional test. Internal program/data buses are completely controllable and observable by the TCU during the test cycle. Diverse test modes of the TCU can increase the test efficiency and also provide complete access to program/data memories for functional test.

This paper proposes a hardware-based parallel pattern matching engine using a memory-based bit-split string matcher architecture. The proposed bit-split string matcher separates the transition table from the state table, so that state transitions towards the initial state are not stored. Therefore, total memory requirements can be minimized.

This paper proposes a built-in self-test (BIST) scheme for noise-tolerant testing of a digital-to-analogue converter (DAC). The proposed BIST calculates the differences in output voltages between a DAC and test modules. These differences are used as the inputs of an integrator that determines integral nonlinearity (INL). The proposed method has an advantage of random noise cancelation and achieves a higher test accuracy than do the conventional BIST methods. The simulation results show high standard noise-immunity and fault coverage for the proposed method.

In this paper, we present an efficient low power scan test technique which simultaneously reduces both average and peak power consumption. The selective scan chain activation scheme removes unnecessary scan chain utilization during the scan shift and capture operations. Statistical scan cell reordering enables efficient scan chain removal. The experimental results demonstrated that the proposed method constantly reduces the average and peak power consumption during scan testing.

This paper proposes a new pattern matching architecture with multi-character processing for deep packet inspection. The proposed pattern matching architecture detects the start point of pattern matching from multi-character input using input text alignment. By eliminating duplicate hardware components using process element tree, hardware cost is greatly reduced in the proposed pattern matching architecture.

Fast string matching is essential for deep packet inspection (DPI). Traditional string matchers cannot keep up with the continuous increases in data rates due to their natural speed limits. We add a multi-byte processing prefilter to the traditional string matcher to detect target patterns on a multiple character basis. The proposed winnowing prefilter significantly reduces the number of identity blocks, thereby reducing the memory requirements.

Although IP address lookup schemes using ternary content addressable memory (TCAM) can perform high speed packet forwarding, TCAM is much more expensive than ordinary memory in implementation cost. As a low-cost solution, binary search algorithms such as a binary trie or a binary search tree have been widely studied. This paper proposes an efficient IP address lookup scheme using balanced binary search with minimal entries and optimal prefix vectors. In the previous scheme with prefix vectors, there were numerous pairs of nearly identical entries with duplicated prefix vectors. In our scheme, these overlapping entries are combined, thereby minimizing entries and eliminating the unnecessary prefix vectors. As a result, the small balanced binary search tree can be constructed and used for a software-based address lookup in small-sized routers. The performance evaluation results show that the proposed scheme offers faster lookup speeds along with reduced memory requirements.

This paper proposes a pattern partitioning algorithm that maps multiple target patterns onto homogeneous memory-based string matchers. The proposed algorithm adopts the greedy search based on lexicographical sorting. By mapping as many target patterns as possible onto each string matcher, the memory requirements are greatly reduced.

This paper presents a low-power implementation scheme of interpolation FIR filters using distributed arithmetic (DA). The key idea of the proposed scheme involves look-up tables generating only nonnegative values. Thus, the proposed scheme can minimize the dynamic power consumption of interpolation FIR filters using DA without additional hardware. When used for implementing a pulse shaping filter for CDMA2000 mobile stations, the proposed filter not only has almost the same hardware complexity as the conventional one; it also has approximately 43% reduced power consumption.

Proposed in this paper is a low power BIST architecture using the pattern mapping method based on the transition freezing method. The transition freezing method generates frozen patterns dynamically according to the transition tendency of an LFSR. This leads to an average power reduction of 60%. However, the patterns have limitations of 100% fault coverage due to random resistant faults. Therefore, in this paper, those faults are detected by mapping useless patterns among frozen patterns to the patterns generated by an ATPG. Throughout the scheme, 100% fault coverage is achieved. Moreover, we have reduced the amount of applied patterns, the test time, and the power dissipation.