Satsuki: An Integrated Processor Synthesis and Compiler Generation System

Barry SHACKLEFORD; Mitsuhiro YASUDA; Etsuko OKUSHI; Hisao KOIZUMI; Hiroyuki TOMIYAMA; Hiroto YASUURA

Satsuki: An Integrated Processor Synthesis and Compiler Generation System

Barry SHACKLEFORD, Mitsuhiro YASUDA, Etsuko OKUSHI, Hisao KOIZUMI, Hiroyuki TOMIYAMA, Hiroto YASUURA

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Entire systems on a chip (SOCs) embodying a processor, memory, and system-specific peripheral hardware are now an everyday reality. The current generation of SOC designers are driven more than ever by the need to lower chip cost, while at the same time being faced with demands to get designs to market more quickly. It was to support this new community of designers that we developed Satsuki-an integrated processor synthesis and compiler generation system. By allowing the designer to tune the processor design to the bitwidth and performance required by the application, minimum cost designs are achieved. Using synthesis to implement the processor in the same technology as the rest of the chip, allows for global chip optimization from the perspective of the system as a whole and assures design portability. The integral compiler generator, driven by the same parameters used for processor synthesis, promotes high-level expression of application algorithms while at the same time isolating the application software from the processor implementation. Synthesis experiments incorporating a 0.8 micron CMOS gate array have produced designs ranging from a 45 MHz, 1,500 gate, 8-bit processor with a 4-word register file to a 31 MHz, 9,800 gate, 32-bit processor with a 16-word register file.

Publication: IEICE TRANSACTIONS on Information Vol.E79-D No.10 pp.1373-1381

Publication Date: 1996/10/25

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Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)

Category: Hardware-Software Codesign

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Barry SHACKLEFORD, Mitsuhiro YASUDA, Etsuko OKUSHI, Hisao KOIZUMI, Hiroyuki TOMIYAMA, Hiroto YASUURA, "Satsuki: An Integrated Processor Synthesis and Compiler Generation System" in IEICE TRANSACTIONS on Information, vol. E79-D, no. 10, pp. 1373-1381, October 1996, doi: .
Abstract: Entire systems on a chip (SOCs) embodying a processor, memory, and system-specific peripheral hardware are now an everyday reality. The current generation of SOC designers are driven more than ever by the need to lower chip cost, while at the same time being faced with demands to get designs to market more quickly. It was to support this new community of designers that we developed Satsuki-an integrated processor synthesis and compiler generation system. By allowing the designer to tune the processor design to the bitwidth and performance required by the application, minimum cost designs are achieved. Using synthesis to implement the processor in the same technology as the rest of the chip, allows for global chip optimization from the perspective of the system as a whole and assures design portability. The integral compiler generator, driven by the same parameters used for processor synthesis, promotes high-level expression of application algorithms while at the same time isolating the application software from the processor implementation. Synthesis experiments incorporating a 0.8 micron CMOS gate array have produced designs ranging from a 45 MHz, 1,500 gate, 8-bit processor with a 4-word register file to a 31 MHz, 9,800 gate, 32-bit processor with a 16-word register file.
URL: https://globals.ieice.org/en_transactions/information/10.1587/e79-d_10_1373/_p

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@ARTICLE{e79-d_10_1373,
author={Barry SHACKLEFORD, Mitsuhiro YASUDA, Etsuko OKUSHI, Hisao KOIZUMI, Hiroyuki TOMIYAMA, Hiroto YASUURA, },
journal={IEICE TRANSACTIONS on Information},
title={Satsuki: An Integrated Processor Synthesis and Compiler Generation System},
year={1996},
volume={E79-D},
number={10},
pages={1373-1381},
abstract={Entire systems on a chip (SOCs) embodying a processor, memory, and system-specific peripheral hardware are now an everyday reality. The current generation of SOC designers are driven more than ever by the need to lower chip cost, while at the same time being faced with demands to get designs to market more quickly. It was to support this new community of designers that we developed Satsuki-an integrated processor synthesis and compiler generation system. By allowing the designer to tune the processor design to the bitwidth and performance required by the application, minimum cost designs are achieved. Using synthesis to implement the processor in the same technology as the rest of the chip, allows for global chip optimization from the perspective of the system as a whole and assures design portability. The integral compiler generator, driven by the same parameters used for processor synthesis, promotes high-level expression of application algorithms while at the same time isolating the application software from the processor implementation. Synthesis experiments incorporating a 0.8 micron CMOS gate array have produced designs ranging from a 45 MHz, 1,500 gate, 8-bit processor with a 4-word register file to a 31 MHz, 9,800 gate, 32-bit processor with a 16-word register file.},
keywords={},
doi={},
ISSN={},
month={October},}

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TY - JOUR
TI - Satsuki: An Integrated Processor Synthesis and Compiler Generation System
T2 - IEICE TRANSACTIONS on Information
SP - 1373
EP - 1381
AU - Barry SHACKLEFORD
AU - Mitsuhiro YASUDA
AU - Etsuko OKUSHI
AU - Hisao KOIZUMI
AU - Hiroyuki TOMIYAMA
AU - Hiroto YASUURA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E79-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 1996
AB - Entire systems on a chip (SOCs) embodying a processor, memory, and system-specific peripheral hardware are now an everyday reality. The current generation of SOC designers are driven more than ever by the need to lower chip cost, while at the same time being faced with demands to get designs to market more quickly. It was to support this new community of designers that we developed Satsuki-an integrated processor synthesis and compiler generation system. By allowing the designer to tune the processor design to the bitwidth and performance required by the application, minimum cost designs are achieved. Using synthesis to implement the processor in the same technology as the rest of the chip, allows for global chip optimization from the perspective of the system as a whole and assures design portability. The integral compiler generator, driven by the same parameters used for processor synthesis, promotes high-level expression of application algorithms while at the same time isolating the application software from the processor implementation. Synthesis experiments incorporating a 0.8 micron CMOS gate array have produced designs ranging from a 45 MHz, 1,500 gate, 8-bit processor with a 4-word register file to a 31 MHz, 9,800 gate, 32-bit processor with a 16-word register file.
ER -