Embedded System Cost Optimization via Data Path Width Adjustment

Barry SHACKLEFORD; Mitsuhiro YASUDA; Etsuko OKUSHI; Hisao KOIZUMI; Hiroyuki TOMIYAMA; Akihiko INOUE; Hiroto YASUURA

Embedded System Cost Optimization via Data Path Width Adjustment

Barry SHACKLEFORD, Mitsuhiro YASUDA, Etsuko OKUSHI, Hisao KOIZUMI, Hiroyuki TOMIYAMA, Akihiko INOUE, Hiroto YASUURA

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Entire systems embedded in a chip and consisting of a processor, memory, and system-specific peripheral hardware are now commonly contained in commodity electronic devices. Cost minimization of these systems is of paramount economic importance to manufactures of these devices. By employing a variable configuration processor in conjunction with a multi-precision compiler generator, we show that there are situations in which considerable system cost reduction can be obtained by synthesizing a CPU that is narrower than the largest variable in the application program.

Publication: IEICE TRANSACTIONS on Information Vol.E80-D No.10 pp.974-981

Publication Date: 1997/10/25

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Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)

Category: High Level Synthesis

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Barry SHACKLEFORD, Mitsuhiro YASUDA, Etsuko OKUSHI, Hisao KOIZUMI, Hiroyuki TOMIYAMA, Akihiko INOUE, Hiroto YASUURA, "Embedded System Cost Optimization via Data Path Width Adjustment" in IEICE TRANSACTIONS on Information, vol. E80-D, no. 10, pp. 974-981, October 1997, doi: .
Abstract: Entire systems embedded in a chip and consisting of a processor, memory, and system-specific peripheral hardware are now commonly contained in commodity electronic devices. Cost minimization of these systems is of paramount economic importance to manufactures of these devices. By employing a variable configuration processor in conjunction with a multi-precision compiler generator, we show that there are situations in which considerable system cost reduction can be obtained by synthesizing a CPU that is narrower than the largest variable in the application program.
URL: https://globals.ieice.org/en_transactions/information/10.1587/e80-d_10_974/_p

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@ARTICLE{e80-d_10_974,
author={Barry SHACKLEFORD, Mitsuhiro YASUDA, Etsuko OKUSHI, Hisao KOIZUMI, Hiroyuki TOMIYAMA, Akihiko INOUE, Hiroto YASUURA, },
journal={IEICE TRANSACTIONS on Information},
title={Embedded System Cost Optimization via Data Path Width Adjustment},
year={1997},
volume={E80-D},
number={10},
pages={974-981},
abstract={Entire systems embedded in a chip and consisting of a processor, memory, and system-specific peripheral hardware are now commonly contained in commodity electronic devices. Cost minimization of these systems is of paramount economic importance to manufactures of these devices. By employing a variable configuration processor in conjunction with a multi-precision compiler generator, we show that there are situations in which considerable system cost reduction can be obtained by synthesizing a CPU that is narrower than the largest variable in the application program.},
keywords={},
doi={},
ISSN={},
month={October},}

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TY - JOUR
TI - Embedded System Cost Optimization via Data Path Width Adjustment
T2 - IEICE TRANSACTIONS on Information
SP - 974
EP - 981
AU - Barry SHACKLEFORD
AU - Mitsuhiro YASUDA
AU - Etsuko OKUSHI
AU - Hisao KOIZUMI
AU - Hiroyuki TOMIYAMA
AU - Akihiko INOUE
AU - Hiroto YASUURA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E80-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 1997
AB - Entire systems embedded in a chip and consisting of a processor, memory, and system-specific peripheral hardware are now commonly contained in commodity electronic devices. Cost minimization of these systems is of paramount economic importance to manufactures of these devices. By employing a variable configuration processor in conjunction with a multi-precision compiler generator, we show that there are situations in which considerable system cost reduction can be obtained by synthesizing a CPU that is narrower than the largest variable in the application program.
ER -