OC-48c High-Speed Network PCI Card: Implementation and Evaluation

Kenji SHIMIZU; Tsuyoshi OGURA; Tetsuo KAWANO; Hiroyuki KIMIYAMA; Mitsuru MARUYAMA

OC-48c High-Speed Network PCI Card: Implementation and Evaluation

Kenji SHIMIZU, Tsuyoshi OGURA, Tetsuo KAWANO, Hiroyuki KIMIYAMA, Mitsuru MARUYAMA

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We have developed an OC-48c (2.4 Gbps) PCI-compliant network interface card and drivers with the aim of evaluating the effectiveness of our proposed link layer protocol MAPOS. In this paper, we study the effectiveness of MAPOS particularly from the viewpoint of the influence of packet sizes up to the 64-kbyte jumbo MTU size and the effectiveness of our new implementation of the non-interrupt-driven sending process and interrupt batching receiving process deployed to improve the throughput in short-packet transmissions. Our main findings are as follows;
Enlarging the packet size up to 64-kbyte MTU improves the performance in transmission. OC-48c wire speed is achieved with packet sizes larger than 16 kbytes.
Implementation of the non-interrupt-driven sending process and the interrupt batching receiving process improves the performance of short-packet transmission. In particular, the transmission throughput is improved by 50% when 64-byte short packets are used. The maximum loss-free receive rate is also raised by 50% when 4-kbyte packets arrive.
With a high-performance CPU, the data-transfer speed of the DMA controller for jumbo packets cannot keep up with the packet-queueing speed of the CPU. Our proposed procedure for adaptive algorithm switching method can resolve this problem.
The maximum TCP throughput observed in our measurement using the latest PCs and MAPOS OC-48c PCI card was 2342.5 Mbps. This throughput represents the highest performance in a legacy-PCI-based system according to the results database of the benchmarking software.

Publication: IEICE TRANSACTIONS on Information Vol.E86-D No.11 pp.2380-2389

Publication Date: 2003/11/01

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Type of Manuscript: Special Section PAPER (Special Issue on New Technologies in the Internet and their Applications)

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Kenji SHIMIZU, Tsuyoshi OGURA, Tetsuo KAWANO, Hiroyuki KIMIYAMA, Mitsuru MARUYAMA, "OC-48c High-Speed Network PCI Card: Implementation and Evaluation" in IEICE TRANSACTIONS on Information, vol. E86-D, no. 11, pp. 2380-2389, November 2003, doi: .
Abstract: We have developed an OC-48c (2.4 Gbps) PCI-compliant network interface card and drivers with the aim of evaluating the effectiveness of our proposed link layer protocol MAPOS. In this paper, we study the effectiveness of MAPOS particularly from the viewpoint of the influence of packet sizes up to the 64-kbyte jumbo MTU size and the effectiveness of our new implementation of the non-interrupt-driven sending process and interrupt batching receiving process deployed to improve the throughput in short-packet transmissions. Our main findings are as follows;
Enlarging the packet size up to 64-kbyte MTU improves the performance in transmission. OC-48c wire speed is achieved with packet sizes larger than 16 kbytes.
Implementation of the non-interrupt-driven sending process and the interrupt batching receiving process improves the performance of short-packet transmission. In particular, the transmission throughput is improved by 50% when 64-byte short packets are used. The maximum loss-free receive rate is also raised by 50% when 4-kbyte packets arrive.
With a high-performance CPU, the data-transfer speed of the DMA controller for jumbo packets cannot keep up with the packet-queueing speed of the CPU. Our proposed procedure for adaptive algorithm switching method can resolve this problem.
The maximum TCP throughput observed in our measurement using the latest PCs and MAPOS OC-48c PCI card was 2342.5 Mbps. This throughput represents the highest performance in a legacy-PCI-based system according to the results database of the benchmarking software.
URL: https://globals.ieice.org/en_transactions/information/10.1587/e86-d_11_2380/_p

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@ARTICLE{e86-d_11_2380,
author={Kenji SHIMIZU, Tsuyoshi OGURA, Tetsuo KAWANO, Hiroyuki KIMIYAMA, Mitsuru MARUYAMA, },
journal={IEICE TRANSACTIONS on Information},
title={OC-48c High-Speed Network PCI Card: Implementation and Evaluation},
year={2003},
volume={E86-D},
number={11},
pages={2380-2389},
abstract={We have developed an OC-48c (2.4 Gbps) PCI-compliant network interface card and drivers with the aim of evaluating the effectiveness of our proposed link layer protocol MAPOS. In this paper, we study the effectiveness of MAPOS particularly from the viewpoint of the influence of packet sizes up to the 64-kbyte jumbo MTU size and the effectiveness of our new implementation of the non-interrupt-driven sending process and interrupt batching receiving process deployed to improve the throughput in short-packet transmissions. Our main findings are as follows;
Enlarging the packet size up to 64-kbyte MTU improves the performance in transmission. OC-48c wire speed is achieved with packet sizes larger than 16 kbytes.
Implementation of the non-interrupt-driven sending process and the interrupt batching receiving process improves the performance of short-packet transmission. In particular, the transmission throughput is improved by 50% when 64-byte short packets are used. The maximum loss-free receive rate is also raised by 50% when 4-kbyte packets arrive.
With a high-performance CPU, the data-transfer speed of the DMA controller for jumbo packets cannot keep up with the packet-queueing speed of the CPU. Our proposed procedure for adaptive algorithm switching method can resolve this problem.
The maximum TCP throughput observed in our measurement using the latest PCs and MAPOS OC-48c PCI card was 2342.5 Mbps. This throughput represents the highest performance in a legacy-PCI-based system according to the results database of the benchmarking software.},
keywords={},
doi={},
ISSN={},
month={November},}

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TY - JOUR
TI - OC-48c High-Speed Network PCI Card: Implementation and Evaluation
T2 - IEICE TRANSACTIONS on Information
SP - 2380
EP - 2389
AU - Kenji SHIMIZU
AU - Tsuyoshi OGURA
AU - Tetsuo KAWANO
AU - Hiroyuki KIMIYAMA
AU - Mitsuru MARUYAMA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E86-D
IS - 11
JA - IEICE TRANSACTIONS on Information
Y1 - November 2003
AB - We have developed an OC-48c (2.4 Gbps) PCI-compliant network interface card and drivers with the aim of evaluating the effectiveness of our proposed link layer protocol MAPOS. In this paper, we study the effectiveness of MAPOS particularly from the viewpoint of the influence of packet sizes up to the 64-kbyte jumbo MTU size and the effectiveness of our new implementation of the non-interrupt-driven sending process and interrupt batching receiving process deployed to improve the throughput in short-packet transmissions. Our main findings are as follows;
Enlarging the packet size up to 64-kbyte MTU improves the performance in transmission. OC-48c wire speed is achieved with packet sizes larger than 16 kbytes.
Implementation of the non-interrupt-driven sending process and the interrupt batching receiving process improves the performance of short-packet transmission. In particular, the transmission throughput is improved by 50% when 64-byte short packets are used. The maximum loss-free receive rate is also raised by 50% when 4-kbyte packets arrive.
With a high-performance CPU, the data-transfer speed of the DMA controller for jumbo packets cannot keep up with the packet-queueing speed of the CPU. Our proposed procedure for adaptive algorithm switching method can resolve this problem.
The maximum TCP throughput observed in our measurement using the latest PCs and MAPOS OC-48c PCI card was 2342.5 Mbps. This throughput represents the highest performance in a legacy-PCI-based system according to the results database of the benchmarking software.
ER -