A C-Testable Multiple-Block Carry Select Adder

Nobutaka KITO; Shinichi FUJII; Naofumi TAKAGI

doi:10.1587/transinf.E95.D.1084

A C-Testable Multiple-Block Carry Select Adder

Nobutaka KITO, Shinichi FUJII, Naofumi TAKAGI

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We propose a C-testable multiple-block carry select adder with respect to the cell fault model. Full adders and 2:1 multiplexers are considered as cells. By an additional external input, we obtain a C-testable carry select adder. We only modify the least significant position of each block. The adder is testable with a test set consisting of 16 patterns regardless of the size of each block and the number of blocks. This is the minimum test set for the adder. We show two gate-level implementations of the adder which are testable with a test set of 9 patterns and 7 patterns respectively, with respect to the single stuck-at fault model.

Publication: IEICE TRANSACTIONS on Information Vol.E95-D No.4 pp.1084-1092

Publication Date: 2012/04/01

Publicized

Online ISSN: 1745-1361

DOI: 10.1587/transinf.E95.D.1084

Type of Manuscript: PAPER

Category: Dependable Computing

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Nobutaka KITO, Shinichi FUJII, Naofumi TAKAGI, "A C-Testable Multiple-Block Carry Select Adder" in IEICE TRANSACTIONS on Information, vol. E95-D, no. 4, pp. 1084-1092, April 2012, doi: 10.1587/transinf.E95.D.1084.
Abstract: We propose a C-testable multiple-block carry select adder with respect to the cell fault model. Full adders and 2:1 multiplexers are considered as cells. By an additional external input, we obtain a C-testable carry select adder. We only modify the least significant position of each block. The adder is testable with a test set consisting of 16 patterns regardless of the size of each block and the number of blocks. This is the minimum test set for the adder. We show two gate-level implementations of the adder which are testable with a test set of 9 patterns and 7 patterns respectively, with respect to the single stuck-at fault model.
URL: https://globals.ieice.org/en_transactions/information/10.1587/transinf.E95.D.1084/_p

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@ARTICLE{e95-d_4_1084,
author={Nobutaka KITO, Shinichi FUJII, Naofumi TAKAGI, },
journal={IEICE TRANSACTIONS on Information},
title={A C-Testable Multiple-Block Carry Select Adder},
year={2012},
volume={E95-D},
number={4},
pages={1084-1092},
abstract={We propose a C-testable multiple-block carry select adder with respect to the cell fault model. Full adders and 2:1 multiplexers are considered as cells. By an additional external input, we obtain a C-testable carry select adder. We only modify the least significant position of each block. The adder is testable with a test set consisting of 16 patterns regardless of the size of each block and the number of blocks. This is the minimum test set for the adder. We show two gate-level implementations of the adder which are testable with a test set of 9 patterns and 7 patterns respectively, with respect to the single stuck-at fault model.},
keywords={},
doi={10.1587/transinf.E95.D.1084},
ISSN={1745-1361},
month={April},}

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TY - JOUR
TI - A C-Testable Multiple-Block Carry Select Adder
T2 - IEICE TRANSACTIONS on Information
SP - 1084
EP - 1092
AU - Nobutaka KITO
AU - Shinichi FUJII
AU - Naofumi TAKAGI
PY - 2012
DO - 10.1587/transinf.E95.D.1084
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E95-D
IS - 4
JA - IEICE TRANSACTIONS on Information
Y1 - April 2012
AB - We propose a C-testable multiple-block carry select adder with respect to the cell fault model. Full adders and 2:1 multiplexers are considered as cells. By an additional external input, we obtain a C-testable carry select adder. We only modify the least significant position of each block. The adder is testable with a test set consisting of 16 patterns regardless of the size of each block and the number of blocks. This is the minimum test set for the adder. We show two gate-level implementations of the adder which are testable with a test set of 9 patterns and 7 patterns respectively, with respect to the single stuck-at fault model.
ER -