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[Author] Daisuke KUROSE(4hit)

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  • A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals

    Akihide SAI  Daisuke KUROSE  Takafumi YAMAJI  Tetsuro ITAKURA  

     
    LETTER

      Vol:
    E91-A No:2
      Page(s):
    557-560

    Sampling clock jitter degrades the dynamic range of an analog-to-digital converter (ADC). In this letter, a low-power low-noise clock signal generator for ADCs is described. As a clock signal generator, a ring-VCO-based charge pump PLL is used to reduce power dissipation within a given jitter specification. The clock signal generator is fabricated on a CMOS chip with 200-MSPS 10-bit ADC. The measured results show that the ADC keeps a 60-MHz input bandwidth and 53-dB dynamic range and a next-generation mobile wireless terminal can be realized with the ADCs and the on-chip low-power clock generator.

  • 55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers

    Tomohiko ITO  Daisuke KUROSE  Takeshi UENO  Takafumi YAMAJI  Tetsuro ITAKURA  

     
    PAPER

      Vol:
    E91-C No:6
      Page(s):
    887-893

    For wireless receivers, low-power 1.2-V 12-bit 100-MSPS pipeline ADCs are fabricated in 90-nm CMOS technology. To achieve low-power dissipation at 1.2 V without the degradation of SNR, the configuration of 2.5 bit/stage is employed with an I/Q amplifier sharing technique. Furthermore, single-stage pseudo-differential amplifiers are used in a Sample-and-Hold (S/H) circuit and a 1st Multiplying Digital-to-Analog Converter (MDAC). The pseudo-differential amplifier with two-gain-stage transimpedance gain-boosting amplifiers realizes high DC gain of more than 90 dB with low power. The measured SNR of the 100-MSPS ADC is 66.7 dB at 1.2-V supply. Under that condition, each ADC dissipates only 55 mW.

  • Low-Power Design of 10-bit 80-MSPS Pipeline ADCs

    Tomohiko ITO  Daisuke KUROSE  Takeshi UENO  Takafumi YAMAJI  Tetsuro ITAKURA  

     
    PAPER-Analog Signal Processing

      Vol:
    E89-A No:7
      Page(s):
    2003-2008

    From the viewpoint of a low-power pipeline ADC design, a comparison between two conventional power reduction techniques is discussed. The comparison shows that the amplifier sharing technique has an advantage in terms of the power reduction effect. To confirm the advantage, a test chip of 10-bit 80-MSPS ADC using the amplifier sharing technique is fabricated. The test chip dissipates 55 mW at 80 MSPS (Mega Sample Per Second).

  • 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters

    Takeshi UENO  Tomohiko ITO  Daisuke KUROSE  Takafumi YAMAJI  Tetsuro ITAKURA  

     
    PAPER

      Vol:
    E91-A No:2
      Page(s):
    454-460

    This paper describes 10-bit, 80-MSample/s pipelined A/D converters for wireless-communication terminals. To reduce power consumption, we employed the I/Q amplifier sharing technique [1] in which an amplifier is used for both I and Q channels. In addition, common-source, pseudo-differential (PD) amplifiers are used in all the conversion stages for further power reduction. Common-mode disturbances are removed by the proposed common-mode feedforward (CMFF) technique without using fully differential (FD) amplifiers. The converter was implemented in a 90-nm CMOS technology, and it consumes only 24 mW/ch from a 1.2-V power supply. The measured SNR and SNDR are 58.6 dB and 52.2 dB, respectively.

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